SOT STT MTJ Architectures for Logic-In-Memory Computing - WebThesis

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SOT STT MTJ Architectures for Logic-In-Memory Computing

Michela Graglia

SOT STT MTJ Architectures for Logic-In-Memory Computing.

Rel. Marco Vacca, Maurizio Zamboni. Politecnico di Torino, Master of science program in Electronic Engineering, 2021

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Abstract

SOT STT MTJ Architectures for Logic-In-Memory Computing

Relators

Marco Vacca, Maurizio Zamboni

Publication type

Electronic

URI

https://webthesis.biblio.polito.it/id/eprint/19227

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