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SOT STT MTJ Architectures for Logic-In-Memory Computing

Michela Graglia

SOT STT MTJ Architectures for Logic-In-Memory Computing.

Rel. Marco Vacca, Maurizio Zamboni. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

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Abstract:

SOT STT MTJ Architectures for Logic-In-Memory Computing

Relators: Marco Vacca, Maurizio Zamboni
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 211
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/19227
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