This thesis covers creating a high-level verification methodology that can be applied to verify the hardware designed with the high-level synthesis methodology. A reusable C++/UVM co-verification framework is implemented to verify a digital signal processor designed in C++ and then synthesized later in RTL and mapped to Verilog. The functional verification of the design is first carried out in the C++ testbench. It is then completed by verifying RTL in the UVM environment while reusing the stimulus generation module written in C++. The Siemens EDA Catapult Coverage (CCOV) is adopted to collect the C++ code coverage. In addition, the Siemens EDA QuestaSim, Visualizer are used at the stage of RTL verification to simulate, debug and generate RTL code coverage.