This thesis focuses on processor functional verification, the DUV(Device Under Verification) here is RISC-V RV32IMFCXpulp. Functional verification ensures that the implementation of a digital design is compliant with specifications before it is mass-produced. Because of the fast growth of device size and complexity, functional verification has become the bottleneck in the design process. Functional verification can take up to 70\% of the time, while the design phase requires around 30\% of the total time. In particular, the device under verification supports I-M-F-C-X extensions which are respectively Base Integer, Integer Multiplication and Division, Single Precision Floating Point, Compressed and PULP-specific. It is clear to understand that the RTL(Register-Transfer-Level) is very complex and as a result, a properly verification framework is necessary.