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Analysis and Design of Compound Semiconductor Stacked Power Amplifiers

Fabio Peinetti

Analysis and Design of Compound Semiconductor Stacked Power Amplifiers.

Rel. Chiara Ramella, Marco Pirola. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

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The thesis concerns the stacked amplifier topology for high frequency applications, and in particular, the goal of the following analysis is the design of a 3-stages stacked amplifier, working at 26 GHz. The possibility to overcome the problem linked to the breakdown voltage limitation on V DS and modularity makes the stacked topology particularly interesting at RF. In particular the output power and gain are directly proportional to the number of stacked stages. From a schematic point of view, a stacked amplifier is made up of a Common Source (CS) and a Pseudo-Common Gate (CG), which corresponds to a Common Gate with a capacitance connected on the its Gate terminal. Two technologies of pHEMT are taken into account and compared in the following discussion: commercial GaN and InGaAs pHEMT processes. Through a load-pull simulation, the optimum load impedance for the GaN is obtained, enhancing a maximum output power of about 32 dBm and a gain of about 12 dB for the single CS stage. An inter-stage matching network (InMN) is necessary between stages, in order to get the maximum output power. As for the 3-stages amplifier the first InMN will be made up of a shunt inductance of 175pH (with a 0.22pF gate capacitance), while for the second one, the best solution seems to be use of a 296 pH shunt inductor (which leads to a Cg = 105 fF). Unfortunately the GaN device results to be unstable out-of-the-band. On the other hand, according load-pull analysis on the GaAs device, it is able to provide a 25dBm maximum output power and a gain of 12.3dB. Also in this case, the best solution for the middle inter-stage matching, resulted to be a 332.3pH shunt inductance, together with a Cg = 0.175pF; the third stage required a C g = 80 fF and a 580 pH shunt inductance. Even if the GaAs device results to be unstable, it can be successfully stabilized. The ideal amplifier is characterized by a gain of 18dB and an output power close to 29dBm. An asymmetrical layout was chosen, in order to enhance compactness and cross-talk immunity. Two layouts, one based on lines and one with lumped inductors were proposed; the use of inductors does not strongly change performance with respect to the previous case, but a more compact layout can be obtained. In particular for a 3-stages GaAs amplifier (with lines) the obtained gain is about 17.29dB, while the corresponding output power is close to 29dBm. The use of real components leads to a narrow-band amplifier, as conformed by frequency simulations in the (24 − 29) GHz. Only around 26 GHz can be profitably used, without a performance worsening.

Relators: Chiara Ramella, Marco Pirola
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 156
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/17872
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