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A Vector Processing Unit implementation for RISC-V Vector Extension: Functional Verification and Assertions on submodules.

Luca Valente

A Vector Processing Unit implementation for RISC-V Vector Extension: Functional Verification and Assertions on submodules.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

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Power dissipation and Energy consumption of digital circuits has emerged as an important design parameter in the evaluation of microelectronic circuits. This has led electronic architects to value Parallel Architectures that allow to perform many calculations, or the execution of processes, simultaneously: exploiting data parallelism reduces instruction bandwidth, reduces required memory bandwidth and lowers the power consumption. A classical example of this trend is the ‘Single Instruction, Multiple Data (SIMD)’ Instruction Set extension which is nowadays implemented in the majority of Instruction Set Architectures. Developing Parallel Architectures that can deliver good performance without the energy and design complexity of higly Out-of-Order superscalar processors is of great interest: Data-parallel applications have had a huge impact not only in highperformance scientific computing but in a diversity of domains such as financial analysis, data-processing, machine learning and many others. An elegant implementation of a Parallel Architecture are Vector Processors: the two main features of Vector Architectures are the presence of a vector register file (VRF), where each vector register can hold a large number of elements , and the presence of many deeply pipelined Functional Units (FU) to directly operate on vectors instead of individual data item. Within the European Processor Initiative (EPI) project, at the Barcelona Supercomputing Center the work is to design a Vector Processing Unit (VPU) to work as a co-processor of a RISC-V based CPU, to allow it to support the RISC-V base vector extension. So far the RISC-V base vector extension is a draft of a stable proposal. It is based on version 0.7.1 which is intended to be stable enough to begin developing toolchains, functional simulators, and initial implementations, though will continue to evolve with minor changes and updates. This Master’s Thesis work has been carried out during an Internship within the Verification Team for the VPU developing. Firstly, we explored the RTL design of the project to understand the behaviours of the whole architecture. As a second step, the goal was to develop solid specifications for some of the submodules of the VPU, observing their desired behaviour in response to the different Vector Instruction. In particular, the work focused on the communication system to move data within the VPU, called Ring. Once the specifications were fixed, it was possible to develop an Assertion-based Verification plan targeting the Ring modules: the whole set of assertions and the assumptions made during this process was included in the simulation test of the whole Architecture in order to ease the research of bugs for the Design Team. In conclusion, it was a 6 month internship that led to several results: - the generation of the specification for different submodules of the Architecture, - the development of different reusable UVM testbenches for these submodules, - the implementation of Formal Verification on the submodules, - the realization of directed binaries for the VPU to stress the Ring modules, - the actualization and design of an Assertion-based Functional Verification Plan able to trace the 36% of bugs relative to the Ring in its functioning period.

Relators: Luciano Lavagno
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 106
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
URI: http://webthesis.biblio.polito.it/id/eprint/16009
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