Gabriele Tombesi
Design and Integration of a Debug Unit for Heterogeneous System-on-Chip Architectures.
Rel. Luciano Lavagno, Luca Carloni. Politecnico di Torino, Master of science program in Nanotechnologies For Icts, 2020
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Abstract
The end of Dennard scaling in the past decade marked the crisis of constant power density scaling across different technology nodes. As a result, the Semiconductor Industry faced an increasing demand for power-efficient systems that promoted the transition from homogeneous to heterogeneous architectures. Heterogeneous systems couple general-purpose processors with a growing number of specialized hardware accelerators that can only execute a few tasks in a very efficient way. Academia put a significant effort in investigating architectures for several domain-specific accelerators and providing innovative solutions addressing the integration challenges in heterogeneous systems. In most of the cases, the ISA of the RISC-V project is leveraged for the processor cores of the platforms proposed.
Among the existing implementations, the Embedded Scalable Platform (ESP) project developed at Columbia University plays a distinctive role
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