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Eliminating Unnecessary Broadcasts to Simplify Out-of-Order Instruction Scheduling

Marco Caccialino

Eliminating Unnecessary Broadcasts to Simplify Out-of-Order Instruction Scheduling.

Rel. Paolo Bernardi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2020

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Abstract:

Over the past decades the industry has been pushing to find ways to achieve better performance and efficiency. The natural evolution of microarchitecture has introduced first the pipeline and then out-of-order superscalar processors to achieve a greater Instruction Level Parallelism. This newer iteration have, on the other hand, increased the complexity of the pipeline stage such as the issue stage. This thesis focus on the above mentioned pipeline stage, analysing which are the aspect that add complexity and energy inefficiency. Using Sniper simulator, an x86 architecture will be used to track the usage of the wake up signal in order to find the instructions that really need to broadcast a signal. Lastly a simple hardware addition will be investigated as a possibility to reduce the broadcast width and simplify the wake up logic.

Relators: Paolo Bernardi
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 52
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Ente in cotutela: Norges Teknisk-Naturvitenskapelige Universitet (NTNU) (NORVEGIA)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/15977
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