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Implementation of a Face Detection Algorithm for Low-Power FPGAs

Giovanni Cappai

Implementation of a Face Detection Algorithm for Low-Power FPGAs.

Rel. Guido Masera, Luca Benini, Michele Magno. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2020

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The recent technological progress is pushing the scientific community for entering a new Artificial Intelligence (AI) era, with systems able to perceive and understand the real world, in order to solve problems in a smarter way than humans do. In this field, Computer Vision (CV) systems are able to automatically see, identify, and understand the external visual world, making decisions depending on the data acquired, emulating the human vision. This progress is placed side by side with a continuous search of hardware architectures, such as GPUs, FPGAs, and ASICs, that can sustain the computation in a more efficient way than conventional software implementations do, allowing the analysis of data directly where it is acquired. The project wants to address both tasks with the implementation of a face detection algorithm, with a Deep Learning approach, on a low power FPGA, taking advantage of its full programmability. While different building blocks have already been demonstrated as independent proofs-of-concept, a fully integrated, stand-alone, system has not been developed and the project tries to fill this hole. This thesis presents the steps performed in order to obtain a suitable face detection algorithm that can fit in a limited memory, low-power FPGA, including pre and post-processing of data. The work can be divided essentially into two parts: firstly a software implementation of the face detector has been done, and the results are compared to the literature, then simplifications are applied to the model in order to reduce its complexity for the successive hardware implementation on the target FPGA.

Relators: Guido Masera, Luca Benini, Michele Magno
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 82
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: ETH - Integrated Systems Laboratory (SVIZZERA)
Aziende collaboratrici: ETH Zurich
URI: http://webthesis.biblio.polito.it/id/eprint/15934
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