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Design and implementation of neural networks on FPGA based on model compression analysis

Gianmarco Canzonieri

Design and implementation of neural networks on FPGA based on model compression analysis.

Rel. Luciano Lavagno, Marisa López-Vallejo. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

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The increasing amount of data available nowadays has made the use of automatic learning algorithms, also known as machine learning, spread. Machine learning is widely used for applications like speech recognition, natural language processing or robotics. The most popular technique used for these purposes are neural networks. These models require a great amount of computation capacity and until now, GPUs have mainly covered these computations. Recently, field programmable gate arrays (FPGAs) are becoming more common within these applications. The main difference between GPUs and FPGAs is that the latter offer the user the possibility of designing specific hardware instead of using a fixed architecture. Also, FPGAs offer a great parallel computation capacity as well as low power consumption compared with GPUs. For this project, it has been decided to analyze the model compression for a neural network in order to understand how model compression can influence the accuracy and as a consequence the improvement in needed hardware and memory constrain. This because computing edge neural network has fixed constrain that it is fundamental to respect. After the extensive model compression operated in MATLAB, there is a design and implemention details part of an optimized neural network on FPGA. We will study the benefits the FPGA provides, paying a special attention to the resources utilization, throughput and accuracy of the algorithm. Experimental results will be carried out on a Xilinx FPGA, in particular, we will use the Zynq-7000 SoC ZC706 Evaluation Kit from Xilinx. This board contains an XC7Z045 FPGA.

Relators: Luciano Lavagno, Marisa López-Vallejo
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 151
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Universidad Politecnica de Madrid
URI: http://webthesis.biblio.polito.it/id/eprint/15332
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