Study and development of a VHDL infrastructure for signals probing of GPGPU architectures - WebThesis

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Study and development of a VHDL infrastructure for signals probing of GPGPU architectures

Salvatore Costa

Study and development of a VHDL infrastructure for signals probing of GPGPU architectures.

Rel. Luca Sterpone, Boyang Du, Matteo Sonza Reorda. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

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Relatori

Luca Sterpone, Boyang Du, Matteo Sonza Reorda

Tipo di pubblicazione

Elettronica

URI

https://webthesis.biblio.polito.it/id/eprint/14558

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