Study and development of a VHDL infrastructure for signals probing of GPGPU architectures - WebThesis

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Study and development of a VHDL infrastructure for signals probing of GPGPU architectures

Salvatore Costa

Study and development of a VHDL infrastructure for signals probing of GPGPU architectures.

Rel. Luca Sterpone, Boyang Du, Matteo Sonza Reorda. Politecnico di Torino, Master of science program in Electronic Engineering, 2020

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Relators

Luca Sterpone, Boyang Du, Matteo Sonza Reorda

Academic year

2019/20

Publication type

Electronic

Number of Pages

169

Course of studies

Master of science program in Electronic Engineering

Classe di laurea

New organization > Master science > LM-29 - ELECTRONIC ENGINEERING

URI

https://webthesis.biblio.polito.it/id/eprint/14558

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