This thesis describes some techniques to be used in EDA synthesis tools to increase the quality of results of digital circuits. We present circuit transformations able to improve the delay by pushing critical signals forward in the logic. The algorithms are applied to netlists of mapped or generic non-sized gates, without electrical optimization. The elaborations we present are graph-based and can be used in conjunction with generic algebraic methods. The first two algorithms rely on the associative and distributive property which are used to restructure a cluster of few gates to reduce the logic levels for critical paths. The last algorithm presents an extension of the Global Flow algorithm.