Simone Alessandro Chiaberto
SoC Silicon Validation: possible approaches and practical results.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020
Abstract
The internship project consists of two main parallel objectives: as first, analyzing the performances of a set of IPs (Intellectual Properties) components (Ethernet, DDR RAMs, SDIO) available on the new under-development SoC by NXP®, the i.MX8DXL. Those performances are specifically related to the type of the peripheral, and are obtained thanks to a remote FPGA-based SoC simulation environment, called ZeBu® and provided by Synopsys®. On top of this, as a second but equally important goal, tests are run both bare-metal and through the usage of a real-time OS, called FreeRTOS™, whose advanced and widespread capabilities may play a crucial role in raising the silicon validation activity on a different perspective.
This duality has been then analyzed, for the sake of the study, to determine if and which one of the two approaches overcome the other in terms of features provided
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