Zaid Rawhi Mohammad Mohaidat
Study of Verification Techniques for Digital Architectures.
Rel. Mariagrazia Graziano, Marco Vacca, Fabrizio Riente. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019
|
Preview |
PDF (Tesi_di_laurea)
- Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives. Download (1MB) | Preview |
Abstract
Nowadays digital systems are continuously growing in complexity and the ASIC industry is struggling to meet schedule. About two thirds of the industry are behind with their planned projects. Similarly, the industry is struggling to keep pace in terms of quality. In accordance with the studies reported in the literature, it can be noticed that there is a gap between the ability to fabricate and manufacture according to Moore’s law and what can actually be designed in reality within a given project schedule. The first study was carried out by ITRS and refers to the productivity gap. The other one is a Collett study that describes functional verification and adoption of technology and again makes reference to the gap between what can be verified and what can be designed.
A lot of organizations used to struggle to adopt advanced techniques: they were still using 1990 best practices in terms of directed tests and code coverage, implying that the industry has not necessarily kept up with verification techniques
Relatori
Anno Accademico
Tipo di pubblicazione
Numero di pagine
Corso di laurea
Classe di laurea
URI
![]() |
Modifica (riservato agli operatori) |
