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Design of the execution pipeline for LEN5, an out-of-order RISC-V processor

Michele Caon

Design of the execution pipeline for LEN5, an out-of-order RISC-V processor.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019

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Abstract:

Design of a RISC-V out-of-order, multiple issue, general purpose processor, with support for an operating system and possibly other ISA defined extensions. The project will be developed and documented on GitHub.
Relators: Maurizio Martina
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 140
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/13205
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