Design of a Low Cost Single Gate Planar Junctionless Transistor over FD-SOI Wafer

Arian Nowbahari

Design of a Low Cost Single Gate Planar Junctionless Transistor over FD-SOI Wafer.

Rel. Matteo Cocuzza. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019

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Abstract:
Relators:	Matteo Cocuzza
Academic year:	2019/20
Publication type:	Electronic
Number of Pages:	122
Subjects:
Corso di laurea:	Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea:	New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela:	University of South-Eastern Norway (NORVEGIA)
Aziende collaboratrici:	UNSPECIFIED
URI:	http://webthesis.biblio.polito.it/id/eprint/12543

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