CMOS technology is the most popular and worldwide spread fabrication methodology employed for the construction of integrated circuits, which are used in practically all the electronic applications. Over the last three decades, CMOS technology has undergone an extraordinary evolution characterized by a continuous downward scaling trend, which has led to an increasingly pronounced miniaturization of devices. Unfortunately, sustaining the downscaling tendency nowadays is becoming more and more challenging, because of two main kinds of limitations which arise during fabrication. The first are physical, since the properties of matter below a certain threshold do not scale together with the physical dimensions. The latter are technological, due to the constraints of traditional top-down approaches; the usage of photolithography, for example, entails problems of misalignment which are not acceptable when the dimensions involved are in the order of few tens of nanometers.