Carlo Ciaccia
Gating of TASE Grown InAs Nanowires for Applications in Fault-Tolerant Topological Quantum Computing.
Rel. Carlo Ricciardi. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2019
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Abstract
In recent years, III-V semiconductor nanowires (NWs) are attracting increasing interest in the scientific world because of the promise to provide value-added functionalities on integrated circuits by means of spintronic components, photonic circuit elements and topological quantum devices. This is mainly thanks to their high carrier mobility and saturation velocity combined with large effective g-factor. The interest of the quantum computing community in these devices stems from the possibility to eventually interface the III-V semiconductor to a superconductor. This combination unlocks the observation and control of new phenomena in mesoscopic physics. Carriers in the semiconductor may inherit certain properties of the superconductor while maintaining semiconducting characteristics such as tunable carrier density, long mean free paths, spin–orbit interaction and large g–factor.
Outstandingly, the combination of gate- and magnetic field-tunability with superconductivity allows to realize a topological state of matter where Majorana Zero Modes (MZMs) are predicted to exist
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