Speed Enhancement Methods for HEVC Interpolation Filters

Video sequences are largely diffused and have several applications worldwide. As a matter of fact, the necessity for a proficient video coding standard is required, by replacing the HM reference model with the HEVC project. The interpolations filters of this system represent the bottleneck for the CPU time: therefore an hardware implementation is strictly necessary in order to fulfill a short time coding requirement. The purpose of this work of thesis is to find an appropriate internal architecture for the adders that are involved in the filtering operation, in order to further increase the throughput of the system. After a first analysis on input data statistics, several techniques are applied to enhance the efficiency of the entire system. Both exact and approximate adders are introduced, with a further examination on the impact of these choices on the performances of the reference system. In the following, Ch.1 aims to give a general introduction of video coding, HEVC interpolation filters and to present the starting hardware reference structure. In Ch.2 parallel-prefix adders topologies are introduced to solve the time efficiency issue for the Chroma Legacy architecture, while Ch.3 explores the adoption of adaptive approximate computing with Generic Accuracy Configurable adders for the Luma Legacy architecture. Finally in Ch.4 the different adders topologies, presented in the previous sections, are applied to the approximate DCT-IF architectures in order to enhance performances.