Specification and Implementation of a Dependable SoC Platform Based on the RISC-V Instruction Set Architecture

In modern System on Chip (SoC) designs, ensuring the reliability and testability of integrated circuits is crucial given their growing complexity. Traditional testing methods are insufficient, requiring advanced Design for Testability (DfT) techniques. The thesis consists in the development of a complex SoC with high reliability and testability without the use of external components. The SoC will allow the final user to run different tests of the platform to ensure the correct behavior of the SoC using an internal processor. The developed system integrates two RISC-V based processors: the Ibex and CVA6 cores. In this SoC, the Ibex processor serves as a test controller for the main CVA6 processor, as well as for memory and other peripheral interfaces, allowing consistent monitoring and testing of key components within the SoC. Redundancy techniques, including Triple Modular Redundancy (TMR) and Error Correction Code (ECC), are applied on critical communication interfaces of the Ibex processor to improve system resilience and fault tolerance. The memory system includes two memory units of 16 KB each. To ensure reliability and enable complete internal testing, a Memory Built-In Self-Test (MBIST) is implemented on the CVA6 core’s memory, controlled by the Ibex processor. Logic Built-In Self-Test (LBIST) is implemented for testing the main CVA6 core. The CVA6 design includes a Internal Scan test mode with 2 scan chains and a Streaming Compression test mode with a scan compressor, decompressor, and 33 scan chains. Strategically placed test points are present in areas with low controllability and observability, thus enhancing test coverage. The LBIST operates with a control key supplied by the Ibex processor, allowing for flexible and programmable testing through specific registers. The results demonstrate that the implemented DfT techniques significantly improve the testability and reliability of the SoC while reducing test time and cost. This work contributes to the ongoing efforts in the semiconductor industry to develop more efficient and effective testing methodologies for complex digital systems.