Integration of LEN5, a RISC-V Out-of-Order Microprocessor, Inside a Low-Power, Heterogeneous System on Chip

Processors that support Out-of-Order (OoO) execution are widely used today, forming the foundation of modern processors. The ability to reorder the execution of instructions makes these processors, already widely adopted in consumer and High-Performance Computing fields, attractive for modern Low-Power Heterogeneous Systems, where it is essential to coordinate a large number of peripherals such as Coprocessors, Accelerators, GPUs, etc., with arbitrary latencies. Being able to execute instructions as soon as their operands are available, rather than in the order specified by the user, helps to mask the latencies of these peripherals while simultaneously increasing Instruction Level Parallelism (ILP), thus enhancing performance. In this context, architectures based on modular ISAs, such as RISC-V, are particularly suited for application-specific scenarios where it is crucial to support custom instructions to accelerate and improve the efficiency of critical parts of selected applications. The work described in this thesis focuses on the development of a module capable of connecting a 64-bit out-of-order RISC-V core, LEN5, to a 32-bit microcontroller platform, X-HEEP, and on the development of internal core modules for supporting the debug system present on the platform itself and similar microcontrollers. The ultimate goal is to create a complete system comprising all components of a Low-Power General-Purpose SoC, such as memories and peripherals, which supports not only the development of the processor but also serves as an environment for hardware and software debugging, allowing for the execution of tests on a system aligned with real-world applications. In the first part of the thesis, the development of a Bridge that handles the conversion of 64-bit core requests into 32-bit requests for the system bus will be presented. The section will begin with an introduction to the architectures involved, LEN5 and X-HEEP, including an overview of the RISC paradigm with relevant historical context and an explanation of its widespread adoption. It will then focus on one of the key points of this thesis: the development process of the bridge module, analyzing its functional requirements, detailing the architectural choices, and describing its internal design in detail. This will be followed by the testing phase, where the module’s correct functionality and the results obtained will be analyzed. Finally, the integration of LEN5 into X-HEEP will be discussed, assessing the impact and performance of the bridge. In the second part of the thesis, the development process of the components necessary for integrating the debug system into LEN5 will be detailed. This section will begin with the development of the modules required to support the JTAG protocol, followed by a focus on the modifications to LEN5's architecture needed for compatibility with the debug module within the X-HEEP platform.