Design and Implementation of Instruction Fusion Techniques in a RISC-V Out-Of-Order core

This thesis explores the design and implementation of instruction fusion techniques in a RISC-V Out-of-Order core. Instruction fusion is a microarchitectural technique that aims at optimising performance by merging multiple instructions inside the processor into a single operation, without modifying the Instruction Set Architecture. The study explores the potential of instruction fusion in optimizing resource utilization, reducing instruction count, and improving execution efficiency within the Lagarto Ox core, developed at the Barcelona Supercomputing Center. The work involves the design of a scalable infrastructure capable of supporting various fusion idioms, initially focusing on compressed instructions with plans for future support of normal-sized instructions. Verification and validation are conducted through custom testbenches, while performance evaluations demonstrate significant reductions in execution cycles and instruction counts. The study concludes with an analysis of the physical design impact, emphasizing the trade-offs in area and frequency for implementing instruction fusion in a RISC-V architecture.