Automation of Delta Sigma Filter Design with High-Level-Synthesis

This thesis presents an innovative exploration of the design process of various digital filter IPs used inside a Delta-Sigma ADC. This work has been carried out in collaboration with \textit{Infineon Technologies, Austria} and it is based on the use of High-Level Synthesis (HLS) to create parameterized and reusable digital filters hardware architectures. In this thesis, we focus on Finite Impulse Response (FIR) filters, Polyphase decimation filters and Cascade Integrator Comb (CIC) decimation filters, which are amongst the most common filter structures used in this type of application. The hardware design of these filters is achieved through Siemens EDA HLS tool ‘Catapult’. HLS is a technology that assists with the transformation of a high-level description of hardware (written in C++ or SystemC) into a synthesized netlist and, as by-product, an RTL model. Although significantly faster than writing RTL code, using a higher abstraction level can still be time consuming when designing specific hardware blocks according to user/customer requirements. To this end, we have tried to take the power of HLS one step further by automating the complete process: from concept design in Matlab to synthesizable netlist, until functional verification of the hardware. Through our research, we aim to make this digital design process smoother, faster and adaptable to quick changes which will allow for shorter concept-synthesis loops.