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Flexible RISC-Based Hardware Accelerators for Random Forests

Yali Kang

Flexible RISC-Based Hardware Accelerators for Random Forests.

Rel. Daniele Jahier Pagliari, Alessio Burrello, Chen Xie. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024

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Abstract:

Hardware accelerators are crucial for achieving the necessary speed in high-accuracy prediction tasks based on Machine Learning models. This thesis focuses in particular on Random Forests (RFs) and introduces two novel accelerator architectures that prioritize flexibility, addressing a significant gap in current designs that struggle with supporting varying model hyper-parameters. By allowing partial programmability of the accelerators through compact RISC-like instructions, the research develops two architectures based on pipelined and parallel processing respectively. A compiler to automatically translate an RF model into accelerator configurations (i.e., instructions) has also been developed. Experimental results on an FPGA platform demonstrate that these architectures can swiftly adapt to a variety of RF models, achieving substantial speed-ups without reconfiguration.

Relatori: Daniele Jahier Pagliari, Alessio Burrello, Chen Xie
Anno accademico: 2023/24
Tipo di pubblicazione: Elettronica
Numero di pagine: 73
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/30837
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