Flexible RISC-Based Hardware Accelerators for Random Forests

Hardware accelerators are crucial for achieving the necessary speed in high-accuracy prediction tasks based on Machine Learning models. This thesis focuses in particular on Random Forests (RFs) and introduces two novel accelerator architectures that prioritize flexibility, addressing a significant gap in current designs that struggle with supporting varying model hyper-parameters. By allowing partial programmability of the accelerators through compact RISC-like instructions, the research develops two architectures based on pipelined and parallel processing respectively. A compiler to automatically translate an RF model into accelerator configurations (i.e., instructions) has also been developed. Experimental results on an FPGA platform demonstrate that these architectures can swiftly adapt to a variety of RF models, achieving substantial speed-ups without reconfiguration.