A Design Space Exploration Tool for LDPC Decoder Architectures in 5G NR Applications

Modern communication systems require sophisticated channel coding to enable high performance and low complexity trade-off implementations. A wide variety of decoding techniques have been proposed throughout the years to meet these requirements, while Moore's law slows down and the improvements in silicon process technology are not sufficient to reach the desired data rates. Low-density parity-check (LDPC) codes are one of the most promising techniques in terms of error-correcting capabilities and throughput performance, but the abundance of existing architectures makes difficult to choose optimal solutions. For this reason, this master thesis proposes a design space exploration tool, having the goal to offer a wide range of possible LDPC decoder architectures, comparing their performances and guiding an hypothetical decoder designer towards an effective implementation. The tool's scope includes partially-parallel architectures implementing Min-sum algorithm and decoding Quasi-cyclic LDPC codes compliant with the 5G New Radio standard, based on base-graph 1. Results are obtained on a 45 nm technology library. The design space variables concern design choices such as scheduling scheme, building blocks' architectures, and techniques such as loop unrolling and pipelining, along with a few system parameters. Estimations of the decoders' characteristics such as area, operating frequency and throughput are provided by the tool, exploiting an architectural model of the decoders, and either the direct synthesis results or an empirical model of the fundamental components of these architectures. The output obtained is a rapid and accurate overview of the decoder architectural solutions, highlighting their advantages and disadvantages.