Enhancing programs for delay test of microprocessors through fault propagation analysis

The presented thesis work is centered on the topic of functional test of microprocessors. Functional test, in particular using Software Test Library (STL), is becoming a standard solution for the online test of safety-critical systems, for instance in the automotive domain. Commercial tools provide scan test patterns, however frequently they are not able to reach the given target fault coverage. Nevertheless, the development of high-quality test programs is considerably more challenging than using commercial tools, therefore new solutions are required to improve the fault coverage guaranteed by a STL. The proposed work focuses on the analysis of the propagation of the faults through the paths of the device under test and tries to propose valid solutions to improve the fault coverage of the tests. First, the thesis describes an approach that identifies the set of sequential cells that captures fault effects before being masked during the propagation towards observable points. In order to reach the target fault coverage, a subset of sequential cells is selected using two different set coverage algorithms, assuming that they can be observed resorting to suitable solutions (for example, existing infrastructures, MISR). Subsequently, the work tries to analyze the execution of the test programs. Particularly, starting from the execution trace of the test program, the source code of the program and a fault dictionary, this approach tries to identify the pieces of source code that generate the hard-to-test faults. The goal of this analysis is to give support to the test engineer indicating which parts of the source code should be modified in order to detect those faults and, consequently, allows improving the STLs. The test of this methodology is not the main goal of this thesis, but it is a starting point for a future work. For the experimental part, the PULPino RISCV architecture has been chosen.