Automotive radar processing optimization by exploiting the hardware accelerator of radar sensor chip

In recent years automotive safety has become more and more important due to the high numbers of fatal accidents. The trend is to automate and enhance the safety technologies in order to assist the driver and avoid dangerous situations. Advanced Driver-Assistance Systems (ADAS) can implement various features such as automatic emergency brake, blind-spot detection, automated highway driving and more. ADAS are based on radar technology since it can effectively detect and locate objects without being affected by low visibility or by bad weather conditions. The most common type of radar for automotive applications adopts linear frequency-modulated continuous waveform and it provides range, velocity and direction of arrival of the detected targets. Several integrated single-chip radar sensors are available in the market, capable of operating in the 76- to 81-GHz band with unprecedented levels of integration in an extremely small form factor. The TI AWR1843 device is a self-contained single-chip radar sensor that provides a 3TX, 4RX system with built-in PLL and A2D converters. It integrates the Digital Signal Processing (DSP) subsystem, a processor subsystem responsible for radio configuration, control, and calibration, an ARM R4F for automotive interfacing, and an hardware accelerator block to perform radar processing saving MIPS on the DSP for higher level algorithms. The scope of this thesis is to optimize the performances of automotive radar application based on the TI AWR1843 by implementing the most demanding processing tasks on the hardware accelerator block instead of the general purpose DSP. The performances are evaluated in terms of the time required to execute the different tasks.