Power consumption measurements during NVM tests and solutions for low power embedded test code development

Every electronic device needs to be tested few and few times before going into the market to assure that it works as expected and it is safe. Testing is a procedure done between every step of the circuit production, from wafer level to the step just before selling the integrated circuit into the market, because first the DUT is tested and more money we can save if it is faulty. There are uncountable parts of a DUT that must be tested and the ones that are analyzed in this work are the flash memories embedded in it. Test the memories is crucial because they are the denser part in an electronic circuit and so the probability of a fault to occur is very high. There are different techniques implemented for testing memories and the most popular one is the Memory Built-In Self Test (MBIST) which consists in designing additional hardware and software features into integrated circuits to allow them to perform self-testing. An effective set of algorithms are used to detect all the faults that could occur inside a memory cell such as stuck-at (SAF), transition delay faults (TDF), coupling (CF) or neighborhood pattern sensitive faults (NPSF). The algorithms are written as test codes by test engineer, they are uploaded in the DUT to correctly perform the required tests. Every test itself consumes a certain amount of power and it is characterized by a test time, the aim of this work is understand at what corresponds the power peaks during the test execution and reduce them as much as possible trying also to reduce the test time. There are many factors that can impact the power consumption, from some hardware parts of the circuit to some software functions, the most easy to modify are the ones related to the software because it is need just to modify the test code instead of rebuild the entire circuit. It has been proved that having a portable test code has an important impact on the power request and so it should be better to have dedicated system, few analysis on that has been made. Moreover it has been proved that it is necessary to do always a cautious choice in the frequency of the polling activity because it has a considerable impact on the power consumption, of course less times it is asked if an actions has finished and less power will be consumed because fewer accesses to the registers will be made. The main power contributions during the test executions have been analyzed , but still some of them remain unclear such as the contribution that comes from the Pump Monitor. Its function is to monitor the load of the pumps to understand if faults have occurred but has been proved that inexplicably if it is enabled the amount of power consumed is lower than the power consumed when it is disabled. All the mentioned and also other analysis with the solutions found to decrease the amount of power consumption are reported in this work.