New techniques for path delay faults functional test

With the advance in silicon technology, recent electronic devices are becoming deeply embedded in extremely dense silicon dies and are required to comply with increasingly strict timing requirements. Under these circumstances, several faults can be induced by different causes, like defects in the manufacturing processes, process variations as well as ageing, workload, crosstalk and many other. Some of these defects can only be exposed by testing the delay characteristics of the circuit, so delay fault models are assuming a much more relevant position in fault analysis. However, delay fault models require much more computational effort with respect to simpler and more widespread fault models when producing the test. Applying the test is also a challenge due to the cost of ATE and the complexity introduced by BIST techniques, which obliges to search for other options. Software Based Self Test is desirable in this context because it allows to apply at-speed tests with no hardware overhead and it can be used even in situations where controllability and observability are reduced. In the context of this thesis, new techniques for delay-oriented online functional testing for embedded systems are proposed, focusing on path delay faults in particular.The study was conducted using a RISC-V based core as benchmark device and has led to achieve a very fast and optimized flow for functional test simulations. It has been shown that, with the presented implementation, in all case studies very high percentages of path delay faults detectable with scan techniques can be also detected with functional tests. Additionally, efforts have been put to identify a relationship among stuck-at, transition delay and path delay fault coverage. Some insights about the functional testability have been extracted by analyzing statistically how many misbehaviours a path delay fault should produce before being functionally observable.