Hardware acceleration for AI, robust pose estimation and neural networks

Hardware acceleration offers great flexibility in terms of data reuse and algorithm implementation. This thesis proposes to import into the FPGA world a high-level algorithm used to improve the reliability of the convolutional neural network for robotics, in particular in the area of the object and pose recognition. First of all, the original algorithm will be analysed to highlight the defects, in terms of parallel computing, and the possible improvements. Secondly, a new computing architecture will be proposed and developed to maximise the performance, pointing out the data reuse inside the algorithm.