Video sequences are largely diffused and have several applications worldwide. As a matter of fact, the necessity for a proficient video coding standard is required, by replacing the HM reference model with the HEVC project. The interpolations filters of this system represent the bottleneck for the CPU time: therefore an hardware implementation is strictly necessary in order to fulfill a short time coding requirement. The purpose of this work of thesis is to find an appropriate internal architecture for the adders that are involved in the filtering operation, in order to further increase the throughput of the system. After a first analysis on input data statistics, several techniques are applied to enhance the efficiency of the entire system.