System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis
Robert Margelli
System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2017
|
Preview |
PDF (Tesi_di_laurea)
- Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives. Download (1MB) | Preview |
Abstract
System-level Design of a Latency-insensitive RISC-V Microprocessor and Optimization via High-level Synthesis
Relatori
Tipo di pubblicazione
URI
 |
Modifica (riservato agli operatori) |
