Actuation control for Flight Control Computer application by using parallel computation via AMD Xilinx Versal AI Engine

The advent of high-performance computing on aircraft computer platforms introduces several design challenges. In particular, digital fly-by-wire Flight Control Computers rely on sophisticated actuation control loop algorithms, which demand significant hardware resources for efficient execution. To address these challenges, the AMD Xilinx Versal ACAP (Adaptive Compute Acceleration Platform) provides a cutting-edge and promising architecture. This FPGA is the industry’s first compute platform that integrates dedicated acceleration engines (AI Engines) for scalar and vector processing, tightly coupled with programmable logic and configurable on-chip connectivity. Such a heterogeneous architecture enables the design of customized, high-performance hardware solutions. This thesis, carried out in collaboration with Leonardo Electronics, investigates the development of digital microarchitectures for airborne electronic modules on the Versal platform, and evaluates their hardware implementation both in standard DSP logic blocks and in AI Engines according to the required operation schedules. In particular, using Vitis Model Composer—a high-level development environment—an actuator control loop has been analyzed and mapped across AI Engines and Programmable Logic, interconnected through the AXI4 protocol. C++ code for AI Engines has been developed, while Programmable Logic VHDL code has been generated via graphical block design. Subsequently, the VCK190 Evaluation Board has been programmed accordingly, and performance has been assessed. The results confirm the feasibility of the proposed implementation and highlight the potential to further generalize the algorithms in order to fully exploit the computational capabilities of the hardware.