ASIC Design-Space Exploration using High-Level Synthesis and Multi-Objective Bayesian Optimization

The design of integrated circuits through high-level synthesis (HLS) involves navigating a vast and highly non-linear parameter space, where design choices such as frequency, loop configurations, and channel parallelism strongly affect performance, area, and energy consumption. Conventional workflows rely heavily on manual tuning and repeated experimentation, making design-space exploration both time-consuming and prone to suboptimal results. This thesis addresses these challenges by proposing a fully automated framework that bridges high-level descriptions and integrated hardware design. The framework integrates electronic design automation (EDA) tools with Bayesian optimization, using Spearmint to intelligently suggest parameter configurations based on synthesis feedback. By closing the loop between optimization and synthesis reports, the system efficiently converges towards Pareto-optimal solutions while drastically reducing the number of iterations compared to exhaustive or heuristic search. Experimental results confirm the validity of the approach, demonstrating its ability to identify high-quality hardware configurations and to reveal parameter relevance, thereby providing valuable insights for future designs. Although a complete validation against exhaustive grid search was not feasible, the outcomes strongly indicate the reliability and practical utility of the proposed methodology.