RISC-V Enabled CGRA SystemC Model for AI and ML Applications

he increasing demand for high-performance computation in fields such as signal processing, scientific computing, and embedded systems has highlighted the need for specialized hardware accelerators. Several architectural solutions exist, including Graphics Processing Units (GPU s), Field Programmable Gate Arrays ( FPGA s), Application Specific Integrated Circuits (ASICs), and Coarse Grained Reconfigurable Architectures (CGRAs). The objective of this thesis is the design of a generic CGRA architecture capable of operating on floating point data. The processing elements within the array support a broad range of functions, including arithmetic operations, Multiply Accumulate ( MAC), direct and inverse trigonometric functions, direct and inverse hyperbolic functions, and exponential functions. For testing and benchmarking, the proposed accelerator model has been in-tegrated into a SystemC open-source model of a RISC-V-based microcontroller through an Advanced eXtensible Interface (AXI ) bus interface. This setup enables the execution of computational kernels and the evaluation of their performance in terms of clock cycles. In conclusion, the proposed model, combined with the systemC platform, has been shown to effectively benchmark and test the execution of Artificial Intelligence( AI )/Machine Learning ( ML ) and automotive applications on highly configurable and parallel architectures as the proposed CGRA.