FPGA implementation of a frequency estimator for RADAR localization applications.

The work presented in this thesis focuses on the design of a 24 GHz Frequency Modulated Continuous Wave (FMCW) radar system for precise target detection and localization in short to medium range distances. Realized with the ADF5901, ADF5904, and ADF4159 chipset, the proposed system takes advantage of the merits of FMCW radar, such as robustness against challenging environmental conditions and the ability to measure target distance and velocity. The modification, a delay line between the RF output and transmit antenna, finding its place in the radar architecture introduces an artificial delay, which should create the impression of a longer distance towards the target, proportionally raising the beat frequency, which is necessary for a better resolution of the FFT-based demodulation process. This approach greatly improves the system's range precision while still allowing the computational complexity to remain reasonable. The careful placement of the delay line at the transmitter side avoids degradation in the SNR, which is often experienced whenever such delays are applied at the receiving end. The thesis also discusses strengths and weaknesses of operating at the 24 GHz frequency. While it offers compact design with adequate range resolution, this frequency range represents a good balance between the lower-frequency radars with poor spatial resolution and the higher-frequency systems that are more complicated and expensive. A very effective compromise, the 24 GHz radar remains for applications involving short range where size and cost sensitivity are important. Most of the work involves designing and implementing the receiver architecture. The system realizes signal conditioning, filtering, decimation, and FFT processing in SystemVerilog. This focuses on architectural parallelism and pipelining for peak performance of the design. Filtering is performed using a third-order Chebyshev filter for effective noise reduction with minimum signal compromise in integrity for demodulation. The FPGA implementation is selected for flexibility and parallel processing capabilities, which are critical in handling high-speed streams of data emanating from the radar. The architecture incorporates a decimation strategy in its design to reduce computational load without sacrificing any aspects of signal fidelity. There is also a custom-designed square root module for efficiently computing the envelope of the signal. These involved extensive simulations and real experiments to validate the system performance, which showed targets detectable within a few centimeters of resolution or even less. Results that meet the designed performance, in terms of precision, speed in processing, and efficiency as a whole, are demonstrated. This makes the radar suitable for applications in areas such as automotive safety and industrial automation. This thesis, therefore, proposes a 24 GHz FMCW radar system, effectively incorporating improvements in range precision using delay line integration and efficient signal processing based on FPGA hardware. The system is able to solve such challenges as the balance between precision and complexity on one side, and cost on the other, while being easily adaptable to a wide variety of real-world sensing applications.