The complexity of EDA tools for ICs are crucial enablers for the semiconductor industry as the size of integrated circuits (ICs) have been increasing enormously. With groundbreaking innovations in IC design and integration, some chips even have up to billions transistors, in the meanwhile the slowing down of Moore's Law have caused that the number of transistors per design increases exponentially and doubles every two years. Consequently, the corresponding design space which originally supposed to be searched for an implementation that satisfies all specifications and then optimizes all related factors concerned as NP-Hardness problem in EDA like power, area, delay (PPA) and runtime, etc.