Analysis and Mitigation of Single Event Transients (SET) effect on RISC-V based FPGA
Aditya Garg
Analysis and Mitigation of Single Event Transients (SET) effect on RISC-V based FPGA.
Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2024
