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Analysis and Mitigation of Single Event Transients (SET) effect on RISC-V based FPGA

Aditya Garg

Analysis and Mitigation of Single Event Transients (SET) effect on RISC-V based FPGA.

Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2024