polito.it
Politecnico di Torino (logo)

Design and Optimization of a Digital-Based Operational Transconductance Amplifier

Claudio Sterlino

Design and Optimization of a Digital-Based Operational Transconductance Amplifier.

Rel. Paolo Stefano Crovetti. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

[img]
Preview
PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (6MB) | Preview
Abstract:

The spreading of IoT (Internet of Things) devices has posed a great challenge to the world of integrated circuit design. Systems need to be increasingly smaller and consume less energy, as they are sometimes powered by small batteries or in combination with energy harvesting devices. Technology scaling has allowed digital circuits to benefit from it. Analog subsystems, on the other hand, represent the bottleneck in terms of power dissipation and occupied area. Operational transconductance amplifiers are essential for building analog subsystems such as filters, front-end signal conditioning circuitry or inter-stage amplificatior for ADCs. To be included in the construction of IoT devices, they must meet the conditions of low power dissipation and small occupied area. Over the years, to reduce the performance gap between analog and digital subsystems, various analog functions have been rethought in digital terms to leverage the technological advancements and digital design flow benefits. For this reason, the concept of DIGOTA (Digital-based Operational Transconductance Amplifier) has been explored. Several research studies and prototypes have demonstrated its compatibility with the specific requirements in the field of IoT (Internet of Things). The objective of this thesis work is to optimize this particular topology by proposing a new input stage based on Floating Inverters (FI). This new stage adds a preamplification and provides the ability to control the common mode at the input without using resistive components. The performance of the circuit has been evaluated after the layout was implemented and parasitic extraction was carried out. Subsequently, Monte Carlo simulations have been conducted to assess the circuit's sensitivity to process variations. The results have then been compared with the state of the art.

Relatori: Paolo Stefano Crovetti
Anno accademico: 2023/24
Tipo di pubblicazione: Elettronica
Numero di pagine: 85
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/28487
Modifica (riservato agli operatori) Modifica (riservato agli operatori)