Optimization and Software/Hardware Implementation of Digital Signal Processing Algorithms for Satellite Transponders

This thesis work is placed in the context of deep space communications, which consist in the transfer of scientific and operational data between ground stations and satellites at considerable distances from the Earth. For this purpose, Argotec has developed the ERMES transponder, based on a Software-Defined Radio (SDR) architecture. The thesis focuses on analyzing and optimizing the design and implementation process of digital signal processing (DSP) algorithms, commonly present inside such devices. The main goal is to establish a standardized methodology for the implementation of SDR components, covering the entire process from design to hardware realization. This is achieved by analyzing and verifying the proposed methodology through the design and implementation of one block of the DSP chain: the phase and frequency estimator. This module is used to perform the carrier synchronization during the reception of signals in deep space. In particular, residual carrier modulated signals are treated in this thesis work. All the development phases are defined and performed. Initially, a frequency estimation technique is selected, among those present in literature. Then, a model is realized to simulate the behavior of the synchronization block using different types of signals. Such model is tested, first in the MATLAB platform, with synthetic inputs, and then in a C++ environment, with real inputs generated through instrumentation. Finally, the algorithm is implemented in hardware as an Intellectual Property (IP) core on an FPGA board, exploiting a High-Level Synthesis (HLS) tool. All the steps of the implementation flow just described are validated by means of analysis, tests and measurements, which are carried out on the theoretical model, on the software simulation and on the hardware implementation. The outputs of each stage are compared in order to verify that they are consistent with each other. Moreover, the performance and the amount of resources used are evaluated, to ensure that the requirements of the radio operations and the FPGA board are respected. The results validate the proposed implementation methodology that can, thus, be used as a standard process in future implementations of DSP algorithms for SDRs.