3D Silicon-based Tunnel FET technology: fabrication process and electrical TCAD simulations

MOSFET devices represented the basis of the electronics, but in the last years the scaling of the dimensions required by the technology caused the appearance of some problems, such as short channel effects and power dissipation. To overcome these drawbacks differ- ent solutions are possible and one of them is to change the nature of the device to TFET. Thanks to different conduction mechanism (tunneling) several advantages can be achieved; the most relevant are lower off-current, and so lower power dissipation, and smaller sub- threshold swing. In this thesis the design and the analysis of TFET devices are discussed through the use of the software Synopsys TCAD Sentaurus, by simulating realistic fabrication processes. The purpose is to investigate structures based on homojunctions and materials commonly used in the production of traditional MOSFET. For this aim a modification of the doping, to take advantage from the tunneling, is performed and a comparison with MOSFET ex- amples present in literature is made, mantaining for all approximately the same channel dimension (50 nm). For simplicity the study starts from the analysis of a planar structure, useful to understand and define the correct models to describe, as close as possible to reality, the electronic transport. The work continues to 3D devices, namely Fin and NSGAA TFETs; the key point is the optimization of the structures with the intention to improve, as much as possible, the behavior of the devices without changing its nature; for this reason several analysis on the effects on the figures of merit (ION , IOF F , SS e VT H ) of the parameters, such as channel length, oxide thickness and so on, are carried out. The results show very promising values for what concern the off current (&#8771; 10&#8722;14A/&#956;m), even if a low on current (&#8771; 10&#8722;9A/&#956;m for a single device) and high SS values (> 100 mV/dec rather than < 66 mV/dec) are obtained, in agreement with the related literature results. Finally a comparison between these optimized structures, other TFETs present in liter- ature and the counterparts MOSFETs are performed in order to understand the validity of this study.