UVM Environment for I3C Target Device

I3C Basic is a scaled-down and less complex version of the powerful, flexible and efficient I3C interface, suitable for a wide range of device connectivity applications, including sensor and memory interfaces. The I3C interface was developed by the MIPI Alliance and is designed to overcome the limitations of the I2C interface, while maintaining backward compatibility. Similar to I2C, devices on the I3C bus communicate in a controller/target environment, where both the controller and target device can initiate communication. In this project, the I3C target device used is the I3CS IP, which supports functions based on the MIPI I3C v.1.1.1. Due to the size and complexity of the project, functional verification becomes a challenge throughout the design flow. For this reason, a suitable verification environment must be developed to accelerate the verification phase. Starting from the architecture study of the target, the objective of this work, performed in collaboration with TDK InvenSense, is to develop a verification environment that can be used to test the correct functioning of the main operations of the I3CS IP target. The testbench environment consists of the VIP block, which simulates the controller, the DUT, i.e. the design under test (IP I3CS), the Register File, which serves as the reference model; and a Scoreboard, which compares the actual values sent by the VIP with the values expected by the Register File. An interface must be defined between the VIP and DUT blocks so that the Controller (VIP) can communicate with the I3CS IP Target (DUT) via two buses, Serial Data (SDA) and Serial Clock (SCL). In this way, the controller can generate stimuli for the DUT to verify its correct behaviour. The verification environment is based on the Universal Verification Methodology (UVM), with the UVM class library adding many automation functions such as sequences and data automation to the System Verilog language. In the UVM environment there are several components that together are responsible for driving the input tests to the DUT (Design Under Test), collecting the output transactions and finally comparing the actual results with the expected ones. To improve the verification of the I3CS IP target, it is necessary to test its functionality outside normal operating conditions by performing appropriate tests, including illegal frames.