Investigation of retention and disturb of the BEOL engineered ferroelectric field effect transistors

Caused by the imperfect screening of polarization the Front end of line (FEOL) ferroelectric field effect transistor (FeFET) as non-volatile memory suffers from low data retention. The main mechanism behind is the depolarization field which counteracts the ferroelectric generated internal field and the back-switches ferroelectric dipoles degrading the memory performance. The FEOL FeFET gate stack is made of metal-ferroelectric-insulator-semiconductor (MFIS) and because of the absence of the metal electrode from semiconductor side it will provide an incomplete charge compensation and thus generating a finite depolarization field. An engineering of FeFET stack is proposed where the back end of line (BEOL) is suggested in which a floating conductive layer is sandwiched between the ferroelectric and insulator. In this thesis, specifically, the analysis of retention in the BEOL FeFET is simulated with GINESTRA modeling platform where metal-ferroelectric-metal-insulator semiconductor (MFMIS) gate stack is introduce to overcome the retention issue of the FEOL equivalent. The operation principles as well as the impact of ferroelectric layer's thickness and of the MFM and MFIS area ratio is investigated in order to optimize the advantage of combining a MFM capacitor on top of MIS FET to improve the memory performance of the device.