DESIGN OF RAD-HARD ANALOG BLOCKS FOR A FULLY INTEGRATED DC-DC CONVERTER

The main activity of CERN (the European Organization for Nuclear Research) consists of collecting and analysing data generated from high energy particle colli- sions to study the fundamental constituents of matter and their interactions. This is done by using sophisticated particle detectors that include various electronic cir- cuits. As any electronic system, efficient power delivery to the detector is crucial. However, extra requirements are imposed by the highly radioactive environment, where radiation doses can reach 1 Grad of Total Ionizing Dose (TID) across the lifetime of the circuit. The lack of commercial solutions necessitates the design of radiation-hard power circuits such as DC-DC converters in order to properly operate in such environment. The powering network to be used in the future LHC (Large Hadron Collider) up- grade will consist of two stages of DC-to-DC conversion. The first stage (48V → 5V) has already been designed while the second stage (5V → 0.9V) is currently under development. This thesis will revolve around the design of analog blocks that are to be used in the second stage of this powering network. The chosen topology for the second stage is a stacked tank converter. It is being implemented in a commercial 28nm CMOS technology and utilizes only core tran- sistors rated for 0.9V. Such devices exhibit a strong tolerance against TID, and therefore no specific radiation hardening is required at the schematic level to miti- gate TID effects. In order to properly operate this converter, several blocks have to be designed. In this thesis, five blocks were designed using core transistors and with supply voltages ranging from 0.9V to 1.8V. Over-voltage and single event effects were taken into account and appropriate protections have been implemented. The designed blocks consist of a capacitor-based level shifter with a range of 0.9V → 5V (max), a resistor-less beta multiplier made up of core transistors (rated for 0.9V) with a supply voltage of 0.9V → 1.8V, along with various over-voltage protections, an error amplifier with a GBW of 238 MHz and a DC gain of 94 dB, and a ramp generator along with a current generator sub-block, which constitute an integral part in the control loop of the converter.