Design and Benchmarking of Low Power, Low Noise and Rad-Hard Comparators for Hybrid Pixel Detector for the Large Hadron Collider Upgrade

Hybrid pixel detectors allow to optimize separately the sensor matrix and the readout Application Specific Integrated Circuit (ASIC). Although the use of this type of detectors was extended to other fields of science by the Medipix collaboration, it is still employed at CERN (the European Organization for Nuclear Research) to assemble trackers for the Large Hadron Collider (LHC) experiments. The electronics associated to CERN detectors operates in a harsh environment, because of high levels of radiation and high magnetic field. LHC detecting systems are constantly object of upgrades to improve their performances in terms of speed, resolution and power consumption. To this end, CERN microelectronics section recently choose a 28nm bulk CMOS technology replacing older nodes in order to develop the next generations of read out ASIC. Thanks to the advantages of miniaturized transistors, a new prototype chip named PicoPix is under development with the aim to achieve a time resolution lower than 30ps for large input charges. A continuous-time discriminator is one of the key blocks of the hybrid pixel detector analog front end. It compares the signal originating from the sensor and amplified by the charge sensitive amplifier, with a threshold set above the intrinsic electronic noise. The output of the comparison must be a logic signal since it will be fed to the digital pixel. Four different topology were explored and compared, through simulations, to fulfil the requirement concerning time, mismatch, area and power consumption. Particular attention was given to the optimization of the jitter, which represents the switching uncertainty in the time domain. Some expedients were employed to make the circuits radiation tolerant. Moreover, a layout was developed for two of the topology considered, to evaluate the effects of parasitics on the jitter performance.