One of the most used techniques for testing digital integrated circuits is functional test, above all during the operative lifetime(in-field test). In this specific case, functional test is performed on PULPINO processor, using an SBST(Software-Based Self-test) approach. On one hand, this kind of technique provides an effective way of testing without area or timing overheads, tipically introduced in DFT(design for testability) techniques; on the other hand, it gets difficulties in developing test programs. This master thesis aims to help the test engineer in developing the test program increasing the observability, in particular, of the transition delay faults, exploiting Modelsim and its functionalities because of the deep internal access the tool has on the DUT.