See the EDA Wiki for upto date information 
   
   http://eda.ee.ethz.ch/index.php/Modelsim

##########################################################################
##
## Running RTL simulation
##

You can use the example script compile_rtl.csh-example, copy and adapt it 
for your own needs. 

 1. Compile the RTL

    > cd modelsim/

    > vlib-10.5a rtl
    
    > vcom-10.5a -work rtl -check_synthesis ../sourcecode/a.vhd
    > vcom-10.5a -work rtl -check_synthesis ../sourcecode/b.vhd

 2. Compile the testbench 

    > vcom-10.5a -work rtl ../sourcecode/tb_util.vhd
    > vcom-10.5a -work rtl ../sourcecode/a_tb.vhd

 2. Run the simulation

    > vsim-10.5a -lib rtl a_tb


##########################################################################
##
## Running Postlayout (gate) simulation with SDF
##

You can use the example script compile_gate.csh-example, copy and adapt it 
for your own needs. 

 
 1. Compile the gatelevel netlist and the testbench
 
    > cd modelsim/

    # Use a new empty library without all the behavioral code from RTL simulation in it
    # preferably compile into a dedicated library
 
    > vlib-10.5a  gate
    > vlog-10.5a  -work gate ../encounter/out/final.v

 2. Compile the testbecnh 

    > vcom-10.5a -work gate ../sourcecode/tb_util.vhd
    > vcom-10.5a -work gate ../sourcecode/testbench.vhd
 
 3. Copy and adapt the simulation sample script
 
    > cd modelsim/
    > cp sim_postlayout.csh-example sim_postlayout.csh
 
    > emacs  sim_postlayout.csh&
 
    #  vsim-10.5a -lib gate -t 1ps \
    #            -L uk65lscllmvbbl_vlog \
    #            -L u065gioll25mvir_vlog \
    #            -sdftyp DUT=../encounter/out/chip.sdf.fixed.gz +sdf_verbose \
    #            -v2k_int_delays +no_neg_tchk +ntc_warn +no_glitch_msg \
    #            tb_chip
 
    Notes:
       o "-t 1ps" sets the simulator time resolution, do not change this!
       
       o Use verilog libraries (-L *_vlog) for core and pad cells/
         Do not include macro cell libraries that are not needed. 

       o "DUT" needs to match the instance name of the chip top-level
         entity which is instantiated in the testbench.

       o "voptargs" are currently set for max. simulation speed, but limited access
         to internal ports/nodes. For full access (but lower simulation speed)
         replace the "voptargs" line with this one: 
         -voptargs="+acc" \
         Note that, this will reduce simulation speed by several factors (4-5x)

       o In some rare cases simulation can fail due to bugs in the optimization,
         so you might want to try with less optimizations, e.g. keep access
         to library cells by adding (multiple -voptargs are allowed) this line:
         -voptargs="+acc=c" \

       o -v2k_int_delays causes interconnect delays to be visible at the load
         module port, i.e. the delay of a wire causes a shift of the waveform
         at the receiving port/pin as you would expect.

       o "tb_chip" needs to match the name of the testbench to be loaded. 

       o To run the whole simulation in batch mode and quit Modelsim
         at the end, add the following line (e.g. before "tb_chip"):
         -c -do "run -all; quit" \
 
 4. Run the simulation
 
    > ./sim_postlayout.csh &
 
    Notes:
       o Begin with a (very) low clock frequency that should easily be
         met by the design. Once the testbench passes, increase the clock 
	 frequency to the projected target speed.

       o Common problems/errors are an inappropriate reset phase and unfortunate
         timing for stimuli application and/or response acquisition.  

       o For debugging, the command "add log -r /*" is sometimes very useful as it
         causes ALL signals/nodes to be recorded, so you never get a "-No Data-"
         when tracing signals. To reduce the (huge) amount of data to be recorded,
         you can issue this command later, i.e. around the simulation time that
         needs closer inspection.
 

##########################################################################
##
## Power postlayout simulation
##

 Start with the postlayout setup, but instead of running the simulation 
 normally, perform the following steps in the modelsim prompt


 4. Set up for power simulation
    
    # first make sure the reset phase is over (replace 100ns with reset time)
    vsim> run 100ns

    # generate the VCD file 
    vsim> vcd file ./vcd/a.vcd

    # specify the signals to be recorded. Make sure "a_tb" and "DUT" match
    # your design.
    vsim> vcd add -r /a_tb/DUT/*
    
    # run the simulation, all the signals will be recorded
    vsim> run -all
    
    # make sure to write the file 
    vsim> vcd flush
      or
    vsim> exit
    

