-- The C compiler identification is GNU 5.2.0
-- The CXX compiler identification is GNU 5.2.0
-- The ASM compiler identification is GNU
-- Found assembler: /auto/gmongelli/ri5cy_gnu_toolchain/bin/riscv32-unknown-elf-gcc
System is unknown to cmake, create:
Platform/Linux-CXX to use this system, please post your config file on discourse.cmake.org so it can be added to cmake
-- Detecting C compiler ABI info
System is unknown to cmake, create:
Platform/Linux-CXX to use this system, please post your config file on discourse.cmake.org so it can be added to cmake
-- Detecting C compiler ABI info - done
-- Check for working C compiler: /auto/gmongelli/ri5cy_gnu_toolchain/bin/riscv32-unknown-elf-gcc - skipped
-- Detecting C compile features
-- Detecting C compile features - done
-- Detecting CXX compiler ABI info
System is unknown to cmake, create:
Platform/Linux-CXX to use this system, please post your config file on discourse.cmake.org so it can be added to cmake
-- Detecting CXX compiler ABI info - done
-- Check for working CXX compiler: /auto/gmongelli/ri5cy_gnu_toolchain/bin/riscv32-unknown-elf-c++ - skipped
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- GCC_MARCH= IMXpulpv2
-- USE_ZERO_RISCY= 0
-- RISCY_RV32F= 0
-- ZERO_RV32M= 0
-- ZERO_RV32E= 0
-- PL_NETLIST= 
-- Configuring done
-- Generating done
-- Build files have been written to: /auto/gmongelli/pulpino/sw/build
Scanning dependencies of target vcompile
[H[J
[0;32m--> Compiling PULPino Platform... [0m


[0;32m--> Compiling PULP IPs libraries... [0m
[0;32m--> Compiling axi_node... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap axi_node_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/axi_node_lib 
Copying /prog/Mentor/2019/ModelSim_SE/modeltech/linux_x86_64/../modelsim.ini to modelsim.ini
Modifying modelsim.ini
[0;32mCompiling component: [0;33m axi_node [0m
[0;31m
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/apb_regs_top.sv(92): (vlog-13314) Defaulting port 'init_START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/apb_regs_top.sv(93): (vlog-13314) Defaulting port 'init_END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/apb_regs_top.sv(94): (vlog-13314) Defaulting port 'init_valid_rule_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/apb_regs_top.sv(95): (vlog-13314) Defaulting port 'init_connectivity_map_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AR.sv(59): (vlog-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AR.sv(60): (vlog-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AR.sv(61): (vlog-13314) Defaulting port 'enable_region_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AW.sv(64): (vlog-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AW.sv(65): (vlog-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AW.sv(66): (vlog-13314) Defaulting port 'enable_region_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(56): (vlog-13314) Defaulting port 'arid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(57): (vlog-13314) Defaulting port 'araddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(58): (vlog-13314) Defaulting port 'arlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(59): (vlog-13314) Defaulting port 'arsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(60): (vlog-13314) Defaulting port 'arburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(62): (vlog-13314) Defaulting port 'arcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(63): (vlog-13314) Defaulting port 'arprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(64): (vlog-13314) Defaulting port 'arregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(65): (vlog-13314) Defaulting port 'aruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(66): (vlog-13314) Defaulting port 'arqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(57): (vlog-13314) Defaulting port 'data_AUX_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(58): (vlog-13314) Defaulting port 'data_ID_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(56): (vlog-13314) Defaulting port 'awid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(57): (vlog-13314) Defaulting port 'awaddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(58): (vlog-13314) Defaulting port 'awlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(59): (vlog-13314) Defaulting port 'awsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(60): (vlog-13314) Defaulting port 'awburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(62): (vlog-13314) Defaulting port 'awcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(63): (vlog-13314) Defaulting port 'awprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(64): (vlog-13314) Defaulting port 'awregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(65): (vlog-13314) Defaulting port 'awuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(66): (vlog-13314) Defaulting port 'awqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(60): (vlog-13314) Defaulting port 'rid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(61): (vlog-13314) Defaulting port 'rdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(62): (vlog-13314) Defaulting port 'rresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(64): (vlog-13314) Defaulting port 'ruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_BW_allocator.sv(59): (vlog-13314) Defaulting port 'bid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_BW_allocator.sv(60): (vlog-13314) Defaulting port 'bresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_BW_allocator.sv(61): (vlog-13314) Defaulting port 'buser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_DW_allocator.sv(60): (vlog-13314) Defaulting port 'wdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_DW_allocator.sv(61): (vlog-13314) Defaulting port 'wstrb_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_DW_allocator.sv(63): (vlog-13314) Defaulting port 'wuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_multiplexer.sv(49): (vlog-13314) Defaulting port 'IN_DATA' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(74): (vlog-13314) Defaulting port 'slave_awid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(75): (vlog-13314) Defaulting port 'slave_awaddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(76): (vlog-13314) Defaulting port 'slave_awlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(77): (vlog-13314) Defaulting port 'slave_awsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(78): (vlog-13314) Defaulting port 'slave_awburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(80): (vlog-13314) Defaulting port 'slave_awcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(81): (vlog-13314) Defaulting port 'slave_awprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(82): (vlog-13314) Defaulting port 'slave_awregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(83): (vlog-13314) Defaulting port 'slave_awuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(84): (vlog-13314) Defaulting port 'slave_awqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(90): (vlog-13314) Defaulting port 'slave_wdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(91): (vlog-13314) Defaulting port 'slave_wstrb_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(93): (vlog-13314) Defaulting port 'slave_wuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(109): (vlog-13314) Defaulting port 'slave_arid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(110): (vlog-13314) Defaulting port 'slave_araddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(111): (vlog-13314) Defaulting port 'slave_arlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(112): (vlog-13314) Defaulting port 'slave_arsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(113): (vlog-13314) Defaulting port 'slave_arburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(115): (vlog-13314) Defaulting port 'slave_arcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(116): (vlog-13314) Defaulting port 'slave_arprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(117): (vlog-13314) Defaulting port 'slave_arregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(118): (vlog-13314) Defaulting port 'slave_aruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(119): (vlog-13314) Defaulting port 'slave_arqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(168): (vlog-13314) Defaulting port 'master_bid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(169): (vlog-13314) Defaulting port 'master_bresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(170): (vlog-13314) Defaulting port 'master_buser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(195): (vlog-13314) Defaulting port 'master_rid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(196): (vlog-13314) Defaulting port 'master_rdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(197): (vlog-13314) Defaulting port 'master_rresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(199): (vlog-13314) Defaulting port 'master_ruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(240): (vlog-13314) Defaulting port 'cfg_START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(241): (vlog-13314) Defaulting port 'cfg_END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(242): (vlog-13314) Defaulting port 'cfg_valid_rule_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(243): (vlog-13314) Defaulting port 'cfg_connectivity_map_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap.sv(83): (vlog-13314) Defaulting port 'cfg_START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap.sv(84): (vlog-13314) Defaulting port 'cfg_END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap.sv(85): (vlog-13314) Defaulting port 'cfg_valid_rule_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap.sv(86): (vlog-13314) Defaulting port 'cfg_connectivity_map_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap_with_slices.sv(86): (vlog-13314) Defaulting port 'cfg_START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap_with_slices.sv(87): (vlog-13314) Defaulting port 'cfg_END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap_with_slices.sv(88): (vlog-13314) Defaulting port 'cfg_valid_rule_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_node_wrap_with_slices.sv(89): (vlog-13314) Defaulting port 'cfg_connectivity_map_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_regs_top.sv(132): (vlog-13314) Defaulting port 'init_START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_regs_top.sv(133): (vlog-13314) Defaulting port 'init_END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_regs_top.sv(134): (vlog-13314) Defaulting port 'init_valid_rule_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_regs_top.sv(135): (vlog-13314) Defaulting port 'init_connectivity_map_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(67): (vlog-13314) Defaulting port 'awid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(68): (vlog-13314) Defaulting port 'awaddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(69): (vlog-13314) Defaulting port 'awlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(70): (vlog-13314) Defaulting port 'awsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(71): (vlog-13314) Defaulting port 'awburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(73): (vlog-13314) Defaulting port 'awcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(74): (vlog-13314) Defaulting port 'awprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(75): (vlog-13314) Defaulting port 'awregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(76): (vlog-13314) Defaulting port 'awuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(77): (vlog-13314) Defaulting port 'awqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(83): (vlog-13314) Defaulting port 'wdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(84): (vlog-13314) Defaulting port 'wstrb_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(86): (vlog-13314) Defaulting port 'wuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(93): (vlog-13314) Defaulting port 'arid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(94): (vlog-13314) Defaulting port 'araddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(95): (vlog-13314) Defaulting port 'arlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(96): (vlog-13314) Defaulting port 'arsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(97): (vlog-13314) Defaulting port 'arburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(99): (vlog-13314) Defaulting port 'arcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(100): (vlog-13314) Defaulting port 'arprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(101): (vlog-13314) Defaulting port 'arregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(102): (vlog-13314) Defaulting port 'aruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(103): (vlog-13314) Defaulting port 'arqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(62): (vlog-13314) Defaulting port 'rid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(63): (vlog-13314) Defaulting port 'rdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(64): (vlog-13314) Defaulting port 'rresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(66): (vlog-13314) Defaulting port 'ruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(71): (vlog-13314) Defaulting port 'bid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(72): (vlog-13314) Defaulting port 'bresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(73): (vlog-13314) Defaulting port 'buser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(123): (vlog-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(124): (vlog-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(125): (vlog-13314) Defaulting port 'enable_region_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
[0;36m--> axi_node compilation complete! [0m
[0;32m--> Compiling apb_node... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_node_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_node_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_node [0m
[0;31m
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/apb/apb_node/apb_node.sv(46): (vlog-13314) Defaulting port 'prdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/apb/apb_node/apb_node.sv(51): (vlog-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/apb/apb_node/apb_node.sv(52): (vlog-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/apb/apb_node/apb_node_wrap.sv(40): (vlog-13314) Defaulting port 'start_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/apb/apb_node/apb_node_wrap.sv(41): (vlog-13314) Defaulting port 'end_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
[0;36m--> apb_node compilation complete! [0m
[0;32m--> Compiling axi_mem_if_DP... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap axi_mem_if_DP_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/axi_mem_if_DP_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m axi_mem_if_DP [0m
[0;31m
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(46): (vlog-13314) Defaulting port 'CH0_AWID_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(47): (vlog-13314) Defaulting port 'CH0_AWADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(48): (vlog-13314) Defaulting port 'CH0_AWLEN_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(49): (vlog-13314) Defaulting port 'CH0_AWSIZE_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(50): (vlog-13314) Defaulting port 'CH0_AWBURST_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(52): (vlog-13314) Defaulting port 'CH0_AWCACHE_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(53): (vlog-13314) Defaulting port 'CH0_AWPROT_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(54): (vlog-13314) Defaulting port 'CH0_AWREGION_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(55): (vlog-13314) Defaulting port 'CH0_AWUSER_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(56): (vlog-13314) Defaulting port 'CH0_AWQOS_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(62): (vlog-13314) Defaulting port 'CH0_WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(63): (vlog-13314) Defaulting port 'CH0_WSTRB_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(65): (vlog-13314) Defaulting port 'CH0_WUSER_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(79): (vlog-13314) Defaulting port 'CH0_ARID_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(80): (vlog-13314) Defaulting port 'CH0_ARADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(81): (vlog-13314) Defaulting port 'CH0_ARLEN_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(82): (vlog-13314) Defaulting port 'CH0_ARSIZE_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(83): (vlog-13314) Defaulting port 'CH0_ARBURST_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(85): (vlog-13314) Defaulting port 'CH0_ARCACHE_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(86): (vlog-13314) Defaulting port 'CH0_ARPROT_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(87): (vlog-13314) Defaulting port 'CH0_ARREGION_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(88): (vlog-13314) Defaulting port 'CH0_ARUSER_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(89): (vlog-13314) Defaulting port 'CH0_ARQOS_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(113): (vlog-13314) Defaulting port 'CH1_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(114): (vlog-13314) Defaulting port 'CH1_wdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(115): (vlog-13314) Defaulting port 'CH1_be_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv(125): (vlog-13314) Defaulting port 'Q' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_multi_bank.sv(60): (vlog-13314) Defaulting port 'LP_WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_multi_bank.sv(124): (vlog-13314) Defaulting port 'Q' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_DP_hybr.sv(60): (vlog-13314) Defaulting port 'LP_WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_DP.sv(59): (vlog-13314) Defaulting port 'LP_WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_DP.sv(130): (vlog-13314) Defaulting port 'HP_WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_SP.sv(48): (vlog-13314) Defaulting port 'WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
[0;36m--> axi_mem_if_DP compilation complete! [0m
[0;32m--> Compiling axi_spi_slave... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap axi_spi_slave_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/axi_spi_slave_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m axi_spi_slave [0m
[0;31m
[0;36m--> axi_spi_slave compilation complete! [0m
[0;32m--> Compiling axi_spi_master... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap axi_spi_master_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/axi_spi_master_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m axi_spi_master [0m
[0;31m
[0;36m--> axi_spi_master compilation complete! [0m
[0;32m--> Compiling apb_uart_sv... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_uart_sv_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_uart_sv_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_uart_sv [0m
[0;31m
[0;36m--> apb_uart_sv compilation complete! [0m
[0;32m--> Compiling apb_gpio... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_gpio_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_gpio_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_gpio [0m
[0;31m
[0;36m--> apb_gpio compilation complete! [0m
[0;32m--> Compiling apb_event_unit... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_event_unit_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_event_unit_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_event_unit [0m
[0;31m
[0;36m--> apb_event_unit compilation complete! [0m
[0;32m--> Compiling apb_spi_master... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_spi_master_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_spi_master_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_spi_master [0m
[0;31m
[0;36m--> apb_spi_master compilation complete! [0m
[0;32m--> Compiling fpu... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap fpu_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/fpu_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m fpu [0m
[0;31m
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/fpu/hdl/fpu_fmac/wallace.sv(36): (vlog-13314) Defaulting port 'Pp_index_DI' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/fpu/hdl/fpu_fmac/wallace.sv(36): (vlog-13314) Defaulting port 'Pp_index_DI' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
[0;36m--> fpu compilation complete! [0m
[0;32m--> Compiling apb_pulpino... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_pulpino_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_pulpino_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_pulpino [0m
[0;31m
[0;36m--> apb_pulpino compilation complete! [0m
[0;32m--> Compiling apb_fll_if... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_fll_if_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_fll_if_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_fll_if [0m
[0;31m
[0;36m--> apb_fll_if compilation complete! [0m
[0;32m--> Compiling core2axi... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap core2axi_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/core2axi_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m core2axi [0m
[0;31m
[0;36m--> core2axi compilation complete! [0m
[0;32m--> Compiling apb_timer... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_timer_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_timer_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_timer [0m
[0;31m
[0;36m--> apb_timer compilation complete! [0m
[0;32m--> Compiling axi2apb... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap axi2apb_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/axi2apb_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m axi2apb [0m
[0;31m
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi2apb/AXI_2_APB.sv(69): (vlog-13314) Defaulting port 'WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi2apb/AXI_2_APB.sv(116): (vlog-13314) Defaulting port 'PRDATA' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi2apb/AXI_2_APB_32.sv(113): (vlog-13314) Defaulting port 'PRDATA' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/axi/axi2apb/axi2apb.sv(68): (vlog-13314) Defaulting port 'WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
[0;36m--> axi2apb compilation complete! [0m
[0;32m--> Compiling apb_i2c... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_i2c_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_i2c_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_i2c [0m
[0;31m
[0;36m--> apb_i2c compilation complete! [0m
[0;32m--> Compiling zero_riscy... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap zero_riscy_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/zero_riscy_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m zeroriscy [0m
[0;31m
[0;32mCompiling component: [0;33m zeroriscy_regfile_rtl [0m
[0;31m
[0;32mCompiling component: [0;33m zeroriscy_vip_rtl [0m
[0;31m
[0;36m--> zero_riscy compilation complete! [0m
[0;32m--> Compiling axi_slice_dc... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap axi_slice_dc_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/axi_slice_dc_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m axi_slice_dc [0m
[0;31m
[0;36m--> axi_slice_dc compilation complete! [0m
[0;32m--> Compiling riscv... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap riscv_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/riscv_lib 
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap riscv_lib_gate /auto/gmongelli/pulpino/vsim/modelsim_libs/riscv_lib_gate 
Modifying modelsim.ini
[0;32mCOMPILING COMPONENT: [0;33m riscV_final [0m
[0;32mCompiling component: [0;33m riscv_regfile_rtl [0m
[0;31m
[0;32mCompiling component: [0;33m riscv_vip_rtl [0m
[0;31m
[0;36m--> riscv compilation complete! [0m
[0;32m--> Compiling apb_uart... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb_uart_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb_uart_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb_uart [0m
[0;31m
[0;36m--> apb_uart compilation complete! [0m
[0;32m--> Compiling axi_slice... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap axi_slice_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/axi_slice_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m axi_slice [0m
[0;31m
[0;36m--> axi_slice compilation complete! [0m
[0;32m--> Compiling adv_dbg_if... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap adv_dbg_if_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/adv_dbg_if_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m adv_dbg_if [0m
[0;31m
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/adv_dbg_if/rtl/adbg_or1k_biu.sv(77): (vlog-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/adv_dbg_if/rtl/adbg_or1k_module.sv(91): (vlog-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/adv_dbg_if/rtl/adbg_top.sv(69): (vlog-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//ips/adv_dbg_if/rtl/adv_dbg_if.sv(36): (vlog-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
[0;36m--> adv_dbg_if compilation complete! [0m
[0;32m--> Compiling apb2per... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap apb2per_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/apb2per_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m apb2per [0m
[0;31m
[0;36m--> apb2per compilation complete! [0m
[0;32m--> Compiling PULPino... [0m
Model Technology ModelSim SE-64 vmap 2019.1 Lib Mapping Utility 2019.01 Jan  1 2019
vmap pulpino_lib /auto/gmongelli/pulpino/vsim/modelsim_libs/pulpino_lib 
Modifying modelsim.ini
[0;32mCompiling component: [0;33m PULPino [0m
[0;31m
[1;33m Compiling for RISCV core [0m
** Warning: /auto/gmongelli/pulpino/vsim/..//rtl/axi_node_intf_wrap.sv(34): (vlog-13314) Defaulting port 'start_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
** Warning: /auto/gmongelli/pulpino/vsim/..//rtl/axi_node_intf_wrap.sv(35): (vlog-13314) Defaulting port 'end_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
[0;36m--> PULPino compilation complete! [0m
[0;32m--> Compiling work.tb... [0m
[0;32mCompiling component: [0;33m work.tb [0m
[0;31m
** Note: (vlog-7082) For C/C++ auto compile, choosing compiler /usr/bin/gcc set by the -dpicpppath switch.
** Note: (vlog-7082) For C/C++ auto compile, choosing compiler /usr/bin/gcc set by the -dpicpppath switch.
[0;36m--> work.tb compilation complete! [0m

[0;32m--> PULPino platform compilation complete! [0m

Built target vcompile
Scanning dependencies of target bench
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Scanning dependencies of target crt0
make[3]: AVERTISSEMENT : le fichier « CMakeFiles/crt0.dir/depend.make » a une date de modification 0,00087 s dans le futur
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make[3]: AVERTISSEMENT : décalage d'horloge détecté. La construction peut être incomplète.
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Scanning dependencies of target string
make[3]: AVERTISSEMENT : le fichier « libs/string_lib/CMakeFiles/string.dir/depend.make » a une date de modification 0,00029 s dans le futur
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Scanning dependencies of target Arduino_separate
make[3]: AVERTISSEMENT : le fichier « libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/depend.make » a une date de modification 0,00052 s dans le futur
[  0%] Building C object libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/src/twi.c.o
[01m[K/auto/gmongelli/pulpino/sw/libs/Arduino_lib/separate_libs/src/twi.c:[m[K In function '[01m[KISR_I2C[m[K':
[01m[K/auto/gmongelli/pulpino/sw/libs/Arduino_lib/separate_libs/src/twi.c:362:6:[m[K [01;35m[Kwarning: [m[Ksuggest explicit braces to avoid ambiguous '[01m[Kelse[m[K' [-Wparentheses]
    if(twi_state == TWI_MTX)
[01;32m[K      ^[m[K
[  0%] Building CXX object libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/src/Wire.cpp.o
[100%] Building CXX object libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/src/SPI.cpp.o
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make[3]: AVERTISSEMENT : décalage d'horloge détecté. La construction peut être incomplète.
[100%] Built target Arduino_separate
Scanning dependencies of target rv_polito.elf
make[3]: AVERTISSEMENT : le fichier « apps/riscv_tests/polito/CMakeFiles/rv_polito.elf.dir/depend.make » a une date de modification 0,00089 s dans le futur
[100%] Building C object apps/riscv_tests/polito/CMakeFiles/rv_polito.elf.dir/test_print.c.o
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[100%] Linking CXX executable rv_polito.elf
make[3]: AVERTISSEMENT : décalage d'horloge détecté. La construction peut être incomplète.
[100%] Built target rv_polito.elf
Scanning dependencies of target rv_polito.bin.cmd
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[100%] Built target rv_polito.bin.cmd
Scanning dependencies of target rv_polito.stim.txt
[100%] Generating rv_polito.s19
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Scanning dependencies of target rv_polito.slm.cmd
[100%] Generating slm_files/l2_ram.slm
[100%] Built target rv_polito.slm.cmd
Scanning dependencies of target rv_polito
[100%] Built target rv_polito
Golden simulation analysis
[  0%] Built target bench
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Scanning dependencies of target rv_polito.links
[100%] Generating modelsim.ini
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[100%] Built target rv_polito.links
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Scanning dependencies of target rv_polito.vsimc
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.75We9yCvE1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.75We9yCvE1/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1718_A1.txt exist
STR_RISCV_CORE_ex_stage_i_alu_i_U2102_A1.txt analysis
[  0%] Built target bench
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[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.amnT5LY5l3/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.amnT5LY5l3/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2272_A1.txt analysis
[  0%] Built target bench
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[100%] Generating waves
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[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Sti4PDh0rK/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Sti4PDh0rK/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1710_A.txt analysis
[  0%] Built target bench
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[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bg83hioZyh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bg83hioZyh/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1710_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Bp7yUPSSE2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Bp7yUPSSE2/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U2429_A2.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DDnkGYeVle/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DDnkGYeVle/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1709_ZN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
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[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.alzGDRtITA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.alzGDRtITA/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1709_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.b5bT9PhGbd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.b5bT9PhGbd/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1835_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UtV52pKhGu/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UtV52pKhGu/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U333_ZN.txt analysis
[  0%] Built target bench
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[100%] Built target Arduino_separate
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9IlCAMKG4F/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9IlCAMKG4F/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U335_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.7zsd065IBs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.7zsd065IBs/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U339_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.lTthcW3UbR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.lTthcW3UbR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U338_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.qIttiDvlgB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.qIttiDvlgB/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U338_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.n73BwVfcR5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.n73BwVfcR5/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U459_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.MWPTyAtVjw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.MWPTyAtVjw/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U459_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.84a5btGbp8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.84a5btGbp8/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1734_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.my8CK4BmCh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.my8CK4BmCh/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U460_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.h037TvUkqy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.h037TvUkqy/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U460_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.mqWMBxd0Pv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.mqWMBxd0Pv/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_29__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UmHGufBfBL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UmHGufBfBL/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U461_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.syWChxslWx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.syWChxslWx/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1890_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.JRimGyTups/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.JRimGyTups/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U461_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ILDvBsansF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ILDvBsansF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U203_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.zFPdWM1fSB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.zFPdWM1fSB/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U268_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Lw6Kkqo3Lm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Lw6Kkqo3Lm/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U6_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DlEL0RjopV/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DlEL0RjopV/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U268_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0EaRux4FFZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0EaRux4FFZ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U203_Z.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.O5NVsxymRu/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.O5NVsxymRu/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U6_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZkLAWrDMkB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZkLAWrDMkB/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U6_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YzmHIp592Q/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YzmHIp592Q/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U462_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sMzllu1bur/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sMzllu1bur/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U269_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.iYFhVFQtHk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.iYFhVFQtHk/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U7_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.E66iLKK9vA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.E66iLKK9vA/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U7_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TEUPJ2JKIt/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TEUPJ2JKIt/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_29__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2BCBIjOXMC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2BCBIjOXMC/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U342_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.E1y8n56OjP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.E1y8n56OjP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_RemSel_SP_reg_QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ofQs0eF1Iy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ofQs0eF1Iy/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U335_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.MpDwObhH6E/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.MpDwObhH6E/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U335_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jtL6gHPmCJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jtL6gHPmCJ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U338_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bsyOS3u4Pa/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bsyOS3u4Pa/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U350_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.OFS9toagF1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.OFS9toagF1/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U352_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VeNXU7Iwio/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VeNXU7Iwio/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U355_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sEAXOxXj6c/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sEAXOxXj6c/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U352_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0v3JLv70pz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0v3JLv70pz/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U362_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3HkhonT1Js/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3HkhonT1Js/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U374_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ndbpa97Y7C/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ndbpa97Y7C/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U379_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.MOmi96kx5t/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.MOmi96kx5t/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U376_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.qyx3YinxiU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.qyx3YinxiU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U376_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.JWrHlgeXUc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.JWrHlgeXUc/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U376_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BOQEueOFUC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BOQEueOFUC/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U382_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.LToilwlM3a/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.LToilwlM3a/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U384_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.MZudyLZ5Et/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.MZudyLZ5Et/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U394_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TjDob2dCDS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TjDob2dCDS/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U399_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Q3nxRCCtjc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Q3nxRCCtjc/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U398_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5bxTWfLofo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5bxTWfLofo/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U398_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Wcbdf1YXC8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Wcbdf1YXC8/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U408_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.d6d4Vtrf2Z/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.d6d4Vtrf2Z/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U411_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.lv8aoxUFka/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.lv8aoxUFka/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U408_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KbpcmWm5Ir/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KbpcmWm5Ir/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U418_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TrXa56CvGJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TrXa56CvGJ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U422_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3oLTNnHgsi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3oLTNnHgsi/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U423_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CRFKtFWW7i/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CRFKtFWW7i/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U422_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.XwDsQUZkRY/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.XwDsQUZkRY/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U422_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VkbjO3cQwo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VkbjO3cQwo/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U426_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4GLn715OIL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4GLn715OIL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U446_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.1RwGVjYu3c/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.1RwGVjYu3c/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U454_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.B7kmq47nFf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.B7kmq47nFf/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U454_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.EBikqncQdf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.EBikqncQdf/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U455_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.zwWmDcgp5d/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.zwWmDcgp5d/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U454_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oUWcVBbKUl/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oUWcVBbKUl/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U457_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.m3XdtZioPz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.m3XdtZioPz/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U458_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.QEEVaYX6Ku/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.QEEVaYX6Ku/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U457_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.k0q54T8iGn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.k0q54T8iGn/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U457_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2YYxe9d1Ub/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2YYxe9d1Ub/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1989_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Qjw6AXn0YZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Qjw6AXn0YZ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2133_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Dz1SplDQVh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Dz1SplDQVh/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2145_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.mFgUO1evXp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.mFgUO1evXp/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2167_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.H2dVkMqRXM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.H2dVkMqRXM/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2250_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2Ob84oTwPM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2Ob84oTwPM/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2313_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.qdfnCntCdC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.qdfnCntCdC/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2372_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DXUefH5id7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DXUefH5id7/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2486_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.PLpsSTasW2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PLpsSTasW2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2518_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2Huakm0xgf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2Huakm0xgf/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2533_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.t7sxUnFyHt/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.t7sxUnFyHt/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U338_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0V3dulzpDO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0V3dulzpDO/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_AReg_DP_reg_1__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jSJyYrPYRN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jSJyYrPYRN/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U344_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fUoOiGpLsP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fUoOiGpLsP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U374_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.yi4hQXmTqU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.yi4hQXmTqU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U374_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xSz5Rxm7l0/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xSz5Rxm7l0/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U375_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.LE4EsOABLP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.LE4EsOABLP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U406_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fFzLhD0dWr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fFzLhD0dWr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U406_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CVsz1iN80t/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CVsz1iN80t/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U407_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rMyw7zQpxm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rMyw7zQpxm/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U426_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.kuHLOq7EXu/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.kuHLOq7EXu/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U426_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3dwc9gsggQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3dwc9gsggQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U427_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.S4WyCtMHRC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.S4WyCtMHRC/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U430_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Z9QYaIBCIG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Z9QYaIBCIG/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U430_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hBMIc24JvA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hBMIc24JvA/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U431_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4kGdxGkbiU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4kGdxGkbiU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1858_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RcHMPkZlAr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RcHMPkZlAr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1920_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.x3k1kK2OQa/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.x3k1kK2OQa/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2007_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Xcn3QrFZug/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Xcn3QrFZug/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2035_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FYuh6DdN8B/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FYuh6DdN8B/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2082_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oR1Yymf64g/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oR1Yymf64g/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2116_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.uQiMviS8Aa/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.uQiMviS8Aa/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2196_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oktAptyKcG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oktAptyKcG/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2297_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fkIlj5guXS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fkIlj5guXS/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2470_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dvxKZd1Jkw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dvxKZd1Jkw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2502_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.F34WbvPp5Y/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.F34WbvPp5Y/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U352_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0Uxk716yEM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0Uxk716yEM/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U366_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.JLywtuG1Uo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.JLywtuG1Uo/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U366_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.WI56bbQN2z/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.WI56bbQN2z/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U367_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.j5OfzckkzU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.j5OfzckkzU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U383_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CDz8jGnxVr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CDz8jGnxVr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U382_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6vJ2Vy4Bia/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6vJ2Vy4Bia/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U382_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ym5Y3CdSvL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ym5Y3CdSvL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U387_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.cpLgMoOSO6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.cpLgMoOSO6/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U384_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YRpwaaR1EE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YRpwaaR1EE/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U408_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.D7HuBrmXBV/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.D7HuBrmXBV/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U418_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.GVu8TdQfQP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.GVu8TdQfQP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U418_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RUxcm9eWe2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RUxcm9eWe2/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_AReg_DP_reg_21__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FuXEFqlq9M/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FuXEFqlq9M/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U419_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2ff6PJjWcy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2ff6PJjWcy/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U432_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9Z9OXE6xTK/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9Z9OXE6xTK/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U462_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3j0xXRRr8m/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3j0xXRRr8m/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U463_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fEP0J3kIxK/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fEP0J3kIxK/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U464_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.f8leXc95z2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.f8leXc95z2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2211_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.WniqhIquZ8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.WniqhIquZ8/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2285_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8230N0x9Nk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8230N0x9Nk/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2414_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ca1kxphPhf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ca1kxphPhf/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2438_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.zOKWpnkRqR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.zOKWpnkRqR/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2454_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KirfTzyCfh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KirfTzyCfh/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U335_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.lbZ9QQaB1C/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.lbZ9QQaB1C/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U338_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.L7Yy1FuYvn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.L7Yy1FuYvn/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U342_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bOudDNDdJx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bOudDNDdJx/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U344_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.S3pb2HeNX6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.S3pb2HeNX6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_28__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YkS1TFrGV7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YkS1TFrGV7/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U344_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KDWjcxlB1u/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KDWjcxlB1u/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U352_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.q7owvn2Qkn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.q7owvn2Qkn/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U358_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dIi4na8VOw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dIi4na8VOw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U362_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.GDnFKPFHQf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.GDnFKPFHQf/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U368_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Vm8DFOhKxB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Vm8DFOhKxB/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U374_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FmMfzEg8vk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FmMfzEg8vk/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U384_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.E0AnVsvKfF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.E0AnVsvKfF/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U390_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.URkLGyIIRP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.URkLGyIIRP/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U394_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.lKywUriB50/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.lKywUriB50/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U400_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KrQ2IXkIiN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KrQ2IXkIiN/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U418_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3b4TarqdcI/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3b4TarqdcI/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U422_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bCYKdmGB9w/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bCYKdmGB9w/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U426_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AMCR33R7Kz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AMCR33R7Kz/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_RemSel_SP_reg_QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Slj6RXkrAS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Slj6RXkrAS/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U432_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AEaSSKt8cN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AEaSSKt8cN/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U448_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HYrDSd9XpB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HYrDSd9XpB/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U451_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.gIbUzxj1Do/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.gIbUzxj1Do/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U448_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eSv9csPnLM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eSv9csPnLM/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U454_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.L66yJ9iTj0/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.L66yJ9iTj0/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U457_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.O8Wk2fX0IQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.O8Wk2fX0IQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U459_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IhVvwgnvLY/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IhVvwgnvLY/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U335_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZdfhSaP41R/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZdfhSaP41R/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U338_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bLel2CVI5P/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bLel2CVI5P/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U342_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dB9BX3SgMP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dB9BX3SgMP/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U342_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YlM1nqNSXl/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YlM1nqNSXl/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U347_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2ofYhLnu2a/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2ofYhLnu2a/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U344_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.si9nyBfdg6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.si9nyBfdg6/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U344_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.vo0YA7a2Iu/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.vo0YA7a2Iu/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U358_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4NwiTAOqXc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4NwiTAOqXc/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U362_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IAyQFQItH8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IAyQFQItH8/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U368_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IkrGdHVO9Z/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IkrGdHVO9Z/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U390_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wMOeMD6iqo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wMOeMD6iqo/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U400_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.LoAysr8nKN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.LoAysr8nKN/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U406_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.LuFgHyhDoG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.LuFgHyhDoG/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U414_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.az4J1JurFE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.az4J1JurFE/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U426_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AhnPgqtEfj/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AhnPgqtEfj/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U430_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DeIAsNqsfO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DeIAsNqsfO/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U432_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HIELvF1LIh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HIELvF1LIh/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U435_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Ow1E69TYtX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Ow1E69TYtX/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U432_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rWkIAXZZ26/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rWkIAXZZ26/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U334_S.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bjeZfsxBNd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bjeZfsxBNd/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U398_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8S25kvJSNL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8S25kvJSNL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1947_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.V4wjxbEKu4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.V4wjxbEKu4/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2184_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.192q5a6Gjo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.192q5a6Gjo/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2338_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.SUMTzQzCr1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.SUMTzQzCr1/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U204_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dsFfwTXioE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dsFfwTXioE/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U448_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.crlrp2bmvP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.crlrp2bmvP/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U351_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.llo62rdQIT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.llo62rdQIT/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U376_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jHmT4lwmiC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jHmT4lwmiC/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U408_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.c9dzPQI3t5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.c9dzPQI3t5/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U440_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.D2tULJfg7i/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.D2tULJfg7i/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U452_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xNJbhk3SOT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xNJbhk3SOT/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U444_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aIavga4VUx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aIavga4VUx/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U446_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AGxvmvczHR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AGxvmvczHR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U436_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hWXb2q9bF7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hWXb2q9bF7/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U433_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hnYSLJWvgq/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hnYSLJWvgq/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U424_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.mv2GWTrk0q/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.mv2GWTrk0q/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U416_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oSBQo6thtB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oSBQo6thtB/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U412_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.cHA87XHSIo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.cHA87XHSIo/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U404_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.7UpIT77vrJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.7UpIT77vrJ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U398_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oQIoYz6f4n/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oQIoYz6f4n/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U380_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.tDciofHEiQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.tDciofHEiQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U377_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Wd8zFvY2aO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Wd8zFvY2aO/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U372_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.d5cfqFOfcc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.d5cfqFOfcc/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U369_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Itee0MUHYt/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Itee0MUHYt/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U364_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.NEZWWmIPgZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.NEZWWmIPgZ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U360_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.X6xqOlEYnE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.X6xqOlEYnE/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U353_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HTrGMxsYKL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HTrGMxsYKL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U350_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.V5oPEpZ0nh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.V5oPEpZ0nh/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U350_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.83GBTu2d89/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.83GBTu2d89/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U345_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Ffw1XDxZ8z/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Ffw1XDxZ8z/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U350_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VVCguGL4hu/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VVCguGL4hu/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U418_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jPP9SsAUZv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jPP9SsAUZv/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U440_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CJLBxtr9DQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CJLBxtr9DQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U448_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YMHLF7RGYQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YMHLF7RGYQ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U382_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rZgQ3nM4XY/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rZgQ3nM4XY/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U430_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.uQfQSYQ3dn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.uQfQSYQ3dn/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U394_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZiC3LyrG9X/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZiC3LyrG9X/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2352_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.P6dwu9XGu2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.P6dwu9XGu2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2387_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.EfT8ZkrwXr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.EfT8ZkrwXr/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U123_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.N3Vo7ceUlU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.N3Vo7ceUlU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U89_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KKg8sqx2ZD/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KKg8sqx2ZD/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U119_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CxzBpfgADi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CxzBpfgADi/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U88_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.T2i7dUIe2Z/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.T2i7dUIe2Z/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U146_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.zkSWELYnxz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.zkSWELYnxz/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U128_A3.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fRI1desA6D/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fRI1desA6D/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U107_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.QplgnOWov8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.QplgnOWov8/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U87_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.h6K8vxb7ot/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.h6K8vxb7ot/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_BReg_DP_reg_20__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4inBSNlXN6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4inBSNlXN6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U102_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HK4TWlMiqX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HK4TWlMiqX/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U106_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.nM4xf3MQU1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.nM4xf3MQU1/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U107_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.d0jVeqAfnr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.d0jVeqAfnr/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U146_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.z7xIr8jfvA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.z7xIr8jfvA/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U98_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.PRpqnGX2q0/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PRpqnGX2q0/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U114_A3.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.NYHPflhm9H/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.NYHPflhm9H/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U150_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Eo3nNWN9zk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Eo3nNWN9zk/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U120_A4.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TkokYBi00f/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TkokYBi00f/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U88_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.1L755gkSU0/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.1L755gkSU0/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U139_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.cg1K5qExtr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.cg1K5qExtr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U139_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KLS12Us1sR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KLS12Us1sR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U92_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.F3VnttkN15/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.F3VnttkN15/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U123_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Rx65Ux5dv9/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Rx65Ux5dv9/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U113_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xoeN883rkn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xoeN883rkn/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U106_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.h5OiXP3oMF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.h5OiXP3oMF/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U88_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.odxKb3lKao/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.odxKb3lKao/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U123_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bN0MiOfc0P/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bN0MiOfc0P/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U147_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5RQuqQ6WwR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5RQuqQ6WwR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U87_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ifHuZMKb50/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ifHuZMKb50/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U137_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ehAOXt9oPx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ehAOXt9oPx/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U134_A4.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.S3IawYRRJo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.S3IawYRRJo/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U85_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4auGQ31Oc2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4auGQ31Oc2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U89_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jDuByu85ze/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jDuByu85ze/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U84_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.yeieEQAGaP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.yeieEQAGaP/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U95_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ieQTvJJLb9/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ieQTvJJLb9/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U119_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3JhfFREBsz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3JhfFREBsz/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U147_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.v1J2UDMQqp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.v1J2UDMQqp/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_28__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sKEyziCNNQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sKEyziCNNQ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U462_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ODDbRHt1Vc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ODDbRHt1Vc/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_28__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.whRmt5VhnO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.whRmt5VhnO/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U344_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.taDhEeBy2p/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.taDhEeBy2p/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_27__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ziHbTmYuud/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ziHbTmYuud/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U350_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.OSSbjfbX3x/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.OSSbjfbX3x/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U463_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.GiFXOCtHmK/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.GiFXOCtHmK/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_27__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wnn1CeCGDS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wnn1CeCGDS/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_28__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.H577Sjuaxe/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.H577Sjuaxe/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U352_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.uI4cWqJFpZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.uI4cWqJFpZ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_27__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.K1Fo0PgwYe/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.K1Fo0PgwYe/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_26__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.M3MvLJNgYV/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.M3MvLJNgYV/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U464_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZVCCAUK2Q4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZVCCAUK2Q4/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_26__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.A5nCl24n14/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.A5nCl24n14/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U465_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.igwWO4g8qd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.igwWO4g8qd/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_25__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.lFwMvSXm9s/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.lFwMvSXm9s/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U358_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.T4HtFx0d0d/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.T4HtFx0d0d/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U465_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.XgsqOl2xWX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.XgsqOl2xWX/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_26__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.S8rFJ0rPoK/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.S8rFJ0rPoK/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_25__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.nhWoN9HQhn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.nhWoN9HQhn/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U466_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.vR2rJWi60p/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.vR2rJWi60p/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_24__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aEO9IrzKPg/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aEO9IrzKPg/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_25__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.zVB1K8ZM2L/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.zVB1K8ZM2L/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_24__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.k6JGjD0fzi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.k6JGjD0fzi/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U466_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.uxYlpnToxB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.uxYlpnToxB/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U362_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UzlxHbSzef/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UzlxHbSzef/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U467_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xZHctL9GPq/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xZHctL9GPq/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_23__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.1LZ7npg3pL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.1LZ7npg3pL/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U467_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KtsmkBZ56U/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KtsmkBZ56U/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_23__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.pvDdrH6SWs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.pvDdrH6SWs/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U366_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.agkJ49Jdft/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.agkJ49Jdft/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U468_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Skx4SZ3hMb/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Skx4SZ3hMb/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_22__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TqNQyNFRjo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TqNQyNFRjo/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_22__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.gNJSmZ0V3B/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.gNJSmZ0V3B/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U368_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wLLGR8oTqA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wLLGR8oTqA/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U468_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.EflqG8RJDe/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.EflqG8RJDe/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_23__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.W5oFhjaZ5D/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.W5oFhjaZ5D/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U469_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KnxKNifhey/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KnxKNifhey/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_21__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.y4rEHBJxMK/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.y4rEHBJxMK/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_21__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jx5s9VUm30/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jx5s9VUm30/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U469_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.SM3eT4TmSC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.SM3eT4TmSC/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_22__QN.txt analysis
[  0%] Built target bench
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[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.maFPMEIf4T/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.maFPMEIf4T/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U374_B1.txt analysis
[  0%] Built target bench
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[  0%] Built target string
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[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VLHuYosEIE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VLHuYosEIE/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U470_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HA5D4xQcWU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HA5D4xQcWU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U470_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wSmHKwpTAr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wSmHKwpTAr/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_21__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eOxTuF9oY2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eOxTuF9oY2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_20__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.tNflbAJEks/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.tNflbAJEks/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_20__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ctcVy9V6pQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ctcVy9V6pQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U376_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UsM6rHhm8b/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UsM6rHhm8b/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U471_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eew0QQQRYF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eew0QQQRYF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_19__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.g98LDkwqp2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.g98LDkwqp2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U382_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZLiDN9sdiw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZLiDN9sdiw/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U471_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.gKyLjW1RpI/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.gKyLjW1RpI/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_20__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AEmpzaycyf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AEmpzaycyf/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_19__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.OrcHpjk9M5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.OrcHpjk9M5/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U472_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.QcCDpqSChG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.QcCDpqSChG/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_19__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.86Vl2y7wzr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.86Vl2y7wzr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_18__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DEuQ6SOarR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DEuQ6SOarR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U472_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hg50HqFDl4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hg50HqFDl4/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_18__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ejzHkj5AsO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ejzHkj5AsO/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U384_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.1bAf2ShzkX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.1bAf2ShzkX/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U473_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HxlVLrCWGl/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HxlVLrCWGl/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U390_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.MuYvrrybYR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.MuYvrrybYR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_18__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FUCUu3SHRz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FUCUu3SHRz/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_17__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.01jmUMrGkZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.01jmUMrGkZ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U473_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.i3Q00ltd6Y/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.i3Q00ltd6Y/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_17__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.pczGKXz5M1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.pczGKXz5M1/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U474_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.SfpV3pmFKJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.SfpV3pmFKJ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_17__QN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5E5hwWnmdN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5E5hwWnmdN/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U474_B1.txt analysis
[  0%] Built target bench
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[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6wIFptSs7L/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6wIFptSs7L/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_16__D.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.40LIdUHfbi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.40LIdUHfbi/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_16__QN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.O5iKKDb2kJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.O5iKKDb2kJ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U394_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.MPtVECWjOL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.MPtVECWjOL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U475_ZN.txt analysis
[  0%] Built target bench
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[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HsxpgDhzZH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HsxpgDhzZH/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_15__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Z1HoPnFqK1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Z1HoPnFqK1/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_15__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aJOv9Min2E/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aJOv9Min2E/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U398_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.olhimp8Flz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.olhimp8Flz/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U475_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FCDq8AAlt7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FCDq8AAlt7/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U476_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.kKtIKXAcJM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.kKtIKXAcJM/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_14__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.O2sMstEz86/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.O2sMstEz86/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_15__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.vkP5IWO8P4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.vkP5IWO8P4/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U476_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Eiyd7aGB3E/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Eiyd7aGB3E/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_14__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0MfCCWrswn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0MfCCWrswn/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U400_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.zsfaxJilwp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.zsfaxJilwp/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U477_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.NpsCpxxnxF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.NpsCpxxnxF/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U477_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BljuTesQBG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BljuTesQBG/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_14__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.7yr4RG8uL4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.7yr4RG8uL4/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_13__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.nYbQeD2cZd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.nYbQeD2cZd/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_13__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FZo9xiUWpX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FZo9xiUWpX/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U406_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2fvraTlSKb/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2fvraTlSKb/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U478_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Pi5XfPNIPv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Pi5XfPNIPv/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U408_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.p3RzmJBzTP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.p3RzmJBzTP/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_12__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.JULU9sG5GE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.JULU9sG5GE/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_13__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.1T0MncXrAH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.1T0MncXrAH/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_12__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Cy4VdsvxwR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Cy4VdsvxwR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U478_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rQvGEToIPI/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rQvGEToIPI/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U479_ZN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ARKcKlEJfY/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ARKcKlEJfY/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_11__D.txt analysis
[  0%] Built target bench
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.T0ey1Euhdc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.T0ey1Euhdc/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U479_B1.txt analysis
[  0%] Built target bench
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[100%] Built target Arduino_separate
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sT2iwqCTTs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sT2iwqCTTs/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U414_B1.txt analysis
[  0%] Built target bench
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[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.WdAC8mhWVi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.WdAC8mhWVi/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_11__Q.txt analysis
[  0%] Built target bench
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[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6Jxd6lfEgh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6Jxd6lfEgh/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_12__QN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.APfFbl6hQn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.APfFbl6hQn/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U480_ZN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FpkpgLqNfx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FpkpgLqNfx/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_11__QN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BSN0qLcQAw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BSN0qLcQAw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_10__D.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.a7ma0vGhHZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.a7ma0vGhHZ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U480_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5rdbBorRHQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5rdbBorRHQ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_10__QN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wodWMED8oe/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wodWMED8oe/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U418_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hXYFZKj7Jw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hXYFZKj7Jw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U481_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Ck2tC1qO0w/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Ck2tC1qO0w/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_9__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eubaz7GTdm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eubaz7GTdm/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U481_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BFUqzYhUpI/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BFUqzYhUpI/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U422_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.uSPIFBfisX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.uSPIFBfisX/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_9__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dBAqcH7Z5H/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dBAqcH7Z5H/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U482_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.SRkrIoJB7G/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.SRkrIoJB7G/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U426_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YvXwXvtniL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YvXwXvtniL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_8__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9Zm2XywwAj/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9Zm2XywwAj/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U482_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6fY46NuEu6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6fY46NuEu6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_8__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fUy4z3ZEy5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fUy4z3ZEy5/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_9__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RTufqTchxS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RTufqTchxS/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U483_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HGX5uzjLnc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HGX5uzjLnc/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_7__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Ze529klbPf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Ze529klbPf/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U483_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.iKhSgfL7XF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.iKhSgfL7XF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_7__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.cTqCQM1Qpx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.cTqCQM1Qpx/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U430_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.voui4tynme/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.voui4tynme/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U484_ZN.txt analysis
[  0%] Built target bench
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[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.gPkIKBM9T6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.gPkIKBM9T6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_7__QN.txt analysis
[  0%] Built target bench
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[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.tseIqvxnV7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.tseIqvxnV7/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U432_B1.txt analysis
[  0%] Built target bench
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[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.50BqKCGeVU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.50BqKCGeVU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U484_B1.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VdFpVcATrL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VdFpVcATrL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_6__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.kNEAWLcYXn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.kNEAWLcYXn/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_6__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.LqzJAx8QM1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.LqzJAx8QM1/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U485_ZN.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.OqORMyhPLj/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.OqORMyhPLj/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U485_B1.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Cz9QnU4rG9/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Cz9QnU4rG9/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_6__QN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.XGKNq8WMGx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.XGKNq8WMGx/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_5__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.27B1m9fqqd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.27B1m9fqqd/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_5__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.JdRKyewn1a/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.JdRKyewn1a/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U438_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oymKBPPB70/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oymKBPPB70/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U486_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dxdDXNPsdR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dxdDXNPsdR/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U487_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AaKlfXqaYd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AaKlfXqaYd/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U486_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.JBDJZmfKa1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.JBDJZmfKa1/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U487_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.gUgswJkFSx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.gUgswJkFSx/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_4__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eOZu9yVYOr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eOZu9yVYOr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U440_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eAQdtZIQKJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eAQdtZIQKJ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_4__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.X7QIpJLzvm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.X7QIpJLzvm/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U489_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AKf3JAtgxe/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AKf3JAtgxe/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U488_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8FDpYSLnNT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8FDpYSLnNT/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_3__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.x3uv2txLdF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.x3uv2txLdF/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U489_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.W5ENJ1AMzP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.W5ENJ1AMzP/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U446_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Yjf5773kJw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Yjf5773kJw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U488_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.mOlWnG1uTE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.mOlWnG1uTE/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_3__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rFHS8Puvgs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rFHS8Puvgs/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U491_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IYznsL1Bv5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IYznsL1Bv5/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U490_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.NJvCc68vGw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.NJvCc68vGw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U490_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.forfk209xJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.forfk209xJ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U448_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oNxWW29RJ0/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oNxWW29RJ0/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_2__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UG40POT9up/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UG40POT9up/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_2__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BthJnME52F/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BthJnME52F/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U491_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.quusJnZcbn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.quusJnZcbn/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U493_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.JVWmhTG6Y1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.JVWmhTG6Y1/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U492_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4WcGaZYXB2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4WcGaZYXB2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_1__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZPblXDxqfT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZPblXDxqfT/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_1__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Sar9R6Bufo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Sar9R6Bufo/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U454_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Nxuvtddmn8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Nxuvtddmn8/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U493_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.lHNVeF0011/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.lHNVeF0011/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U492_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xwKL5aDSS2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xwKL5aDSS2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U495_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aVzWNv9lyH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aVzWNv9lyH/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U494_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.atAhR2RFv9/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.atAhR2RFv9/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U460_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5365fBRwty/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5365fBRwty/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U462_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.7i6xVagcsq/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.7i6xVagcsq/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U463_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0qtEBgMn3l/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0qtEBgMn3l/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U464_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.GyWkINsBCi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.GyWkINsBCi/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U465_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IW7Xy10Swm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IW7Xy10Swm/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U466_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.OkOpo4ATPH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.OkOpo4ATPH/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U467_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.haOlPlfocr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.haOlPlfocr/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U468_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HfLcHXAMMy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HfLcHXAMMy/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U469_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wLDrpx3eNQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wLDrpx3eNQ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U470_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BTdwZaZdnD/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BTdwZaZdnD/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U471_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.GS9u9J0yRU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.GS9u9J0yRU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U472_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.r09IG4qdeU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.r09IG4qdeU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U473_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.PaZ4IcKClH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PaZ4IcKClH/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U474_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dR3S1gbTbL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dR3S1gbTbL/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U475_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VO0sUREUBi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VO0sUREUBi/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U476_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Fb9NoI74Jp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Fb9NoI74Jp/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U477_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.iztvJ1BLuV/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.iztvJ1BLuV/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U478_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3AyE7GTqcP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3AyE7GTqcP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U479_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.nnBdabdya8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.nnBdabdya8/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U480_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BwsymV6Zrp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BwsymV6Zrp/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U481_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.kbEhWt5TKF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.kbEhWt5TKF/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U482_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AUbiv99kkM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AUbiv99kkM/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U483_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.EU7foAaFvU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.EU7foAaFvU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U484_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2kgbsAnI0H/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2kgbsAnI0H/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U485_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UrAZZnzhYQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UrAZZnzhYQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U486_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2P5zP9pmw5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2P5zP9pmw5/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U488_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RHndQOz2oo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RHndQOz2oo/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U490_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.G7tzLQmnHb/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.G7tzLQmnHb/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U492_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.NLRZismOYR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.NLRZismOYR/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U494_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.1YWm3IxtZO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.1YWm3IxtZO/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U494_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6Byvb5rWpy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6Byvb5rWpy/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U495_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Nn7CzyFYMN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Nn7CzyFYMN/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_27__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AUixa46X7K/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AUixa46X7K/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U350_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8pvaQCEw98/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8pvaQCEw98/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_26__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KkuMkzVfbo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KkuMkzVfbo/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U352_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.a9NKTsvfvm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.a9NKTsvfvm/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_25__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wpI5axaNbT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wpI5axaNbT/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U358_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.U6avIqzhdN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.U6avIqzhdN/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U362_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.L6Ab5PohJL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.L6Ab5PohJL/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_23__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TVnZ7p11og/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TVnZ7p11og/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U366_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xHmncoHbqH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xHmncoHbqH/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U368_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hXDmluP9fE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hXDmluP9fE/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_22__Q.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.yAbMSgn9hl/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.yAbMSgn9hl/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U374_B1.txt analysis
[  0%] Built target bench
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[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ulbkxLZp3K/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ulbkxLZp3K/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_21__Q.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eDUrqJmmK6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eDUrqJmmK6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U376_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fMJiz30yOb/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fMJiz30yOb/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_20__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.A5BtpGjcUf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.A5BtpGjcUf/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_19__Q.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.h4lm1kmdd4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.h4lm1kmdd4/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U382_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.PKyNzhWZGg/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PKyNzhWZGg/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_18__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.l6wnZVCH8i/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.l6wnZVCH8i/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U384_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.77ODbiDbJu/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.77ODbiDbJu/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_17__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2yEBZ7oVCg/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2yEBZ7oVCg/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U390_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6JoruDpiU6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6JoruDpiU6/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U394_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3blK0iJmgf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3blK0iJmgf/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_15__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.n9uEd7y1Ld/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.n9uEd7y1Ld/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U398_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sfbMP1zOXQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sfbMP1zOXQ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_14__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HZCbtvqqM3/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HZCbtvqqM3/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U400_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.H44CfzjYO2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.H44CfzjYO2/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_13__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.guxldQ9KQo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.guxldQ9KQo/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U406_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9xq2PSEkDl/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9xq2PSEkDl/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_12__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
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[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.cS20H5dsOd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.cS20H5dsOd/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U408_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.iUfmc8HYUT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.iUfmc8HYUT/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U414_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.tzrd9RGQpC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.tzrd9RGQpC/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_11__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aP4UEinYTZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aP4UEinYTZ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U418_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0XhCQxgH6V/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0XhCQxgH6V/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_9__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.QsyD0FPV5d/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.QsyD0FPV5d/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U422_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IvsjO5DodL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IvsjO5DodL/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U426_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4rYsSGLmZ1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4rYsSGLmZ1/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_7__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.LAfw4EznSs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.LAfw4EznSs/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U430_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.75S8y8KDh6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.75S8y8KDh6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_6__Q.txt analysis
[  0%] Built target bench
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9WZ0XbGXK3/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9WZ0XbGXK3/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U432_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.g2uiV0wUvg/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.g2uiV0wUvg/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U438_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fqPFf8E8Ce/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fqPFf8E8Ce/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U440_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6CzeIJHcJq/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6CzeIJHcJq/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U446_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.mvfHIIwaHg/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.mvfHIIwaHg/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U448_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.7upvrmtpMi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.7upvrmtpMi/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U454_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.F1YGGjTgdK/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.F1YGGjTgdK/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U495_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BihgEQDpe5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BihgEQDpe5/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U457_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CEHITsTBh6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CEHITsTBh6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_0__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.O8ujdFCxh1/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.O8ujdFCxh1/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_0__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4zP4LxrcsY/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4zP4LxrcsY/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U494_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Nub0CLWbWG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Nub0CLWbWG/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U366_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.GVU2EZhfdg/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.GVU2EZhfdg/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U384_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RrjJAIgLpQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RrjJAIgLpQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U438_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RXUabncwil/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RXUabncwil/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U132_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.R5ASjWWojD/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.R5ASjWWojD/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U103_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Y5kq9JY5gE/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Y5kq9JY5gE/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U132_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dvgHZ9Oqcv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dvgHZ9Oqcv/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_BReg_DP_reg_0__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ndnUxlsbok/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ndnUxlsbok/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U101_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wlluVMX3W8/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wlluVMX3W8/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U88_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.x5PMdnO5lU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.x5PMdnO5lU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U134_A3.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.d9SbyoIDfw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.d9SbyoIDfw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U333_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.PI2ZHlkHtc/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PI2ZHlkHtc/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_BReg_DP_reg_0__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.arpyGZ6u29/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.arpyGZ6u29/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_0__Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sfQR05wPnF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sfQR05wPnF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResReg_DP_reg_0__D.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DqHnbXKmj2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DqHnbXKmj2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U494_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.XV7MG0ZEVz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.XV7MG0ZEVz/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U495_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Iv4E3laO94/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Iv4E3laO94/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U457_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.7mVMI1SXri/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.7mVMI1SXri/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U184_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.zM5Ubb50dg/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.zM5Ubb50dg/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U173_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.pPhlFRtytN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.pPhlFRtytN/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U186_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.SKAo9eLgmS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.SKAo9eLgmS/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U174_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9b7Qsd3tra/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9b7Qsd3tra/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U167_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.LZzCELjSOP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.LZzCELjSOP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U166_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Cswk5euzUN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Cswk5euzUN/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U169_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Dlbfq1YCCh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Dlbfq1YCCh/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U170_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UI2gxF94as/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UI2gxF94as/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U179_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.erzFAmCP5t/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.erzFAmCP5t/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U185_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BBczbBQBnv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BBczbBQBnv/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U185_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Y3qt19YdaL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Y3qt19YdaL/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U174_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.SzNm2woOl3/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.SzNm2woOl3/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U188_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Rnzu0zjx7V/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Rnzu0zjx7V/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U179_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fmjLFfdlh3/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fmjLFfdlh3/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U169_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5Us27FFl46/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5Us27FFl46/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U167_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.pNJKvSPrmj/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.pNJKvSPrmj/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U170_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8PDinIRiAW/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8PDinIRiAW/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U173_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.uolpR5urx2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.uolpR5urx2/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U184_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xnwtrOy2Kw/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xnwtrOy2Kw/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U166_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.N1YUf2MLrL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.N1YUf2MLrL/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U186_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UCBqvy8DU3/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UCBqvy8DU3/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U337_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6ABKugEgqY/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6ABKugEgqY/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U341_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5ud8ZDTeWR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5ud8ZDTeWR/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U346_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aullTncR5G/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aullTncR5G/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U349_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.vEaNfDfjqr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.vEaNfDfjqr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U354_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Uu6BOzGda6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Uu6BOzGda6/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U357_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wi8rDtGhQk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wi8rDtGhQk/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U361_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xQf4XHDy6n/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xQf4XHDy6n/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U365_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Ii43OU471q/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Ii43OU471q/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U370_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.S2jaxOBtGs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.S2jaxOBtGs/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U373_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZQsGfxf1XH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZQsGfxf1XH/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U378_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.mOK3vIoKXy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.mOK3vIoKXy/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U381_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sk4RMpdQLB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sk4RMpdQLB/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U386_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5QDm7J2VNZ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5QDm7J2VNZ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U389_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.i95KHkjgM4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.i95KHkjgM4/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U393_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YTO9RvF8vy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YTO9RvF8vy/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U397_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.yBrAD1gqsH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.yBrAD1gqsH/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U402_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.L1kqGslZJT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.L1kqGslZJT/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U405_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5YjScua7eO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5YjScua7eO/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U410_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.scvtTQ2wVm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.scvtTQ2wVm/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U413_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.SjPbiBvIhv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.SjPbiBvIhv/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U417_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.V9TFjWSGUF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.V9TFjWSGUF/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U421_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ybMyaYHAW6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ybMyaYHAW6/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U425_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.R8rI2HVd1f/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.R8rI2HVd1f/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U429_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.V3W1mjuN6Z/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.V3W1mjuN6Z/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U434_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jXF1WUIPNo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jXF1WUIPNo/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U437_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9q22tIBifD/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9q22tIBifD/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U442_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.o4kTLeZdYP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.o4kTLeZdYP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U445_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FiuAQAJrud/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FiuAQAJrud/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U450_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.V4XUyGsMXf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.V4XUyGsMXf/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_ResInv_SP_reg_Q.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hCvJdlObKq/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hCvJdlObKq/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U453_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.btR97yPZGM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.btR97yPZGM/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U456_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rSrI65xkYT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rSrI65xkYT/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U86_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DdpsZy80mA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DdpsZy80mA/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U114_A4.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.kwmo8mVwfI/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.kwmo8mVwfI/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U105_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.nyZSbCXGQk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.nyZSbCXGQk/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U96_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.9RTZdKuMhl/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.9RTZdKuMhl/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U97_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TzZS3nqGfp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TzZS3nqGfp/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U84_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.a3RY6aNUxS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.a3RY6aNUxS/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U113_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.gnaF2XF2ZV/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.gnaF2XF2ZV/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U84_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8QwSKXhtp4/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8QwSKXhtp4/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U96_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UQAFCtJHix/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UQAFCtJHix/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U456_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.PuhPbg6UNB/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PuhPbg6UNB/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U452_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CkFxrKCCll/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CkFxrKCCll/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U449_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.CkqxJncH9A/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.CkqxJncH9A/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U444_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8sturCxwS7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8sturCxwS7/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U441_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.T5NKp6TKSy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.T5NKp6TKSy/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U436_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.j1QpDw8yOs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.j1QpDw8yOs/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U428_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Z8GcREZkII/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Z8GcREZkII/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U420_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.gDODbbNot9/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.gDODbbNot9/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U412_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZysPklHHEp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZysPklHHEp/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U409_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.2Sy6zGtXwp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.2Sy6zGtXwp/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U404_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bcyEVgQeoz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bcyEVgQeoz/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U401_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KofcuaSniR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KofcuaSniR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U396_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.hCdx7w0wL0/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.hCdx7w0wL0/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U392_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VtqN7iJ67j/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VtqN7iJ67j/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U388_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.WSqIshF3R3/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.WSqIshF3R3/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U385_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UgimPVXVKM/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UgimPVXVKM/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U380_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.c3YgmRlRoj/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.c3YgmRlRoj/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U372_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bLQpNeMxdv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bLQpNeMxdv/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U356_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.FkYvYDbtNU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FkYvYDbtNU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U348_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.qdPCzsZ51C/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.qdPCzsZ51C/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U340_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.VqDeEvN0FF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.VqDeEvN0FF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U99_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8bYpP8l1dy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8bYpP8l1dy/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U100_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6pscruBkYH/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6pscruBkYH/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U99_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ybNda9UXmy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ybNda9UXmy/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U102_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.NSs5NXYj3I/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.NSs5NXYj3I/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_int_div_div_i_U103_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.q30UGDl5dA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.q30UGDl5dA/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1574_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.dBbjM2Rv3l/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.dBbjM2Rv3l/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1973_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.V3sF5PCsuv/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.V3sF5PCsuv/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U278_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.pSWTw7w7jU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.pSWTw7w7jU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U318_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IdJqTHyOx0/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IdJqTHyOx0/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U2276_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TEj481Jj5H/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TEj481Jj5H/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U195_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.T6WqfAVbQm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.T6WqfAVbQm/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U240_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.vt5dGVIGyk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.vt5dGVIGyk/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U195_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.QAk7UDt6IF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.QAk7UDt6IF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U303_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.kC5Jda5Y4G/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.kC5Jda5Y4G/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U195_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.fDeVUReb5I/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.fDeVUReb5I/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U200_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IYHz5fMY3S/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IYHz5fMY3S/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U238_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jCIFz7goGq/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jCIFz7goGq/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U200_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.4SmgfrTvbI/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.4SmgfrTvbI/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U275_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DgEz1ldZO2/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DgEz1ldZO2/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U226_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.whfrfUvrMG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.whfrfUvrMG/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U226_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rHxPuY5Itp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rHxPuY5Itp/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U275_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.kKmuVI0qMk/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.kKmuVI0qMk/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U206_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BIPQ5Vr7ZA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BIPQ5Vr7ZA/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U207_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aWqLKF3Ygn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aWqLKF3Ygn/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U206_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.IxBKVHnjNx/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IxBKVHnjNx/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U265_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.DC1Cdi72wn/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.DC1Cdi72wn/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U206_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.aB9pzwNt0Z/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.aB9pzwNt0Z/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U208_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.89WTHCDdKO/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.89WTHCDdKO/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U208_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.0uQXs0YAKm/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.0uQXs0YAKm/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U206_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UukLOqtiWz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UukLOqtiWz/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U207_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
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[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.PYMYb0h0qF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PYMYb0h0qF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U208_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.BuP9wNoQcp/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.BuP9wNoQcp/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U207_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.HybVov2dqb/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.HybVov2dqb/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U265_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UTjR9JfhHW/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UTjR9JfhHW/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U138_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.S5jEuIKm8r/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.S5jEuIKm8r/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U128_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.G5yzBdVCox/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.G5yzBdVCox/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U138_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.URwCgb2Fu5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.URwCgb2Fu5/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U128_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.oGtEPl4cqU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.oGtEPl4cqU/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U256_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.sDRJ9AMNkt/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.sDRJ9AMNkt/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U138_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Epzy5rFS4E/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Epzy5rFS4E/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U129_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8EqhBHHGGQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8EqhBHHGGQ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U142_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5UhTLomNsr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5UhTLomNsr/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U142_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.41gm3uAIe7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.41gm3uAIe7/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U142_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.A2Lud4bYHo/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.A2Lud4bYHo/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U256_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.6vzBIxexPT/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.6vzBIxexPT/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U138_B.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.AVJblyejW7/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.AVJblyejW7/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U141_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8Y8HdzQonQ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8Y8HdzQonQ/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U141_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3A75DthCno/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3A75DthCno/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U141_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TQUKzSb35u/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TQUKzSb35u/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U127_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.nP5ObPQoBa/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.nP5ObPQoBa/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U127_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Dgy7EYw5hN/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Dgy7EYw5hN/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U137_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.TxH8UfgCJS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.TxH8UfgCJS/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U137_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.1V7kb6GUY6/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.1V7kb6GUY6/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U2497_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UIC37dv6wD/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UIC37dv6wD/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1782_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.nL4NMJ8tvP/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.nL4NMJ8tvP/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1792_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Xii5GMBsVi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Xii5GMBsVi/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1787_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.eVzjBr0YPu/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.eVzjBr0YPu/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1789_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.86h5uTFvmf/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.86h5uTFvmf/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1787_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.KGSDlo5bnU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.KGSDlo5bnU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1816_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.P4hIQJySGG/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.P4hIQJySGG/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1792_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.bKEOqh0QOD/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.bKEOqh0QOD/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1787_C1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.7rlT1Furot/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.7rlT1Furot/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1791_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Ubhdn6hjp5/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Ubhdn6hjp5/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_alu_ff_i_U38_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.x88kuejy2a/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.x88kuejy2a/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_alu_ff_i_U39_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.XNugzyppBz/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.XNugzyppBz/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_alu_ff_i_U38_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.rlmftWHOml/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.rlmftWHOml/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1891_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.vBAq9qenud/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.vBAq9qenud/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U82_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.S7qqz9Dnl9/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.S7qqz9Dnl9/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U996_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.UrJJTiWJUA/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.UrJJTiWJUA/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U996_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.jz4Snc6tfy/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.jz4Snc6tfy/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_alu_ff_i_U4_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.xH4HaLL8nh/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.xH4HaLL8nh/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U997_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.8pC33YVXQV/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.8pC33YVXQV/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U997_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.3idtVlgIJr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.3idtVlgIJr/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U996_ZN.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.wmjpnM1MTF/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.wmjpnM1MTF/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1336_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.YDVjJmVzmt/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.YDVjJmVzmt/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U619_A2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.yEe9QUFZVW/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.yEe9QUFZVW/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1488_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.OnQn5kUdtX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.OnQn5kUdtX/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1488_B2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.NazgGtlGdS/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.NazgGtlGdS/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1410_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.5uQRpT7caC/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.5uQRpT7caC/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1266_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.MiDAQbhw1T/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.MiDAQbhw1T/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1400_A1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RILzWkamDi/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RILzWkamDi/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1531_C2.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.GooCToKsPe/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.GooCToKsPe/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U793_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.k0Gu65qnMJ/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.k0Gu65qnMJ/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1733_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.Y8fVLHjSNX/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.Y8fVLHjSNX/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1919_A.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.96k6aMseUU/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.96k6aMseUU/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U1997_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.vE4S1cfhGW/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.vE4S1cfhGW/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U1980_B1.txt analysis
[  0%] Built target bench
[  0%] Built target crt0
[  0%] Built target string
[  0%] Built target sys
[  0%] Built target Arduino_core
[100%] Built target Arduino_separate
[100%] Built target rv_polito.elf
[100%] Built target rv_polito.slm.cmd
[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ZsFP2DJfMd/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ZsFP2DJfMd/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U744_B1.txt analysis
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« /tmp/tmp.M1cWiiSGMs/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.M1cWiiSGMs/fixed.evcd » supprimé
STR_RISCV_CORE_ex_stage_i_alu_i_U739_B1.txt analysis
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« /tmp/tmp.FIPXJffq7x/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.FIPXJffq7x/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U635_A1.txt analysis
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« /tmp/tmp.IETrbK69Jr/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.IETrbK69Jr/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U714_A1.txt analysis
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« /tmp/tmp.PWkEGFUmpq/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PWkEGFUmpq/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U744_A1.txt analysis
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[100%] Generating vectors/stim.txt
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« /tmp/tmp.PQBJA9g1OV/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.PQBJA9g1OV/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U624_A1.txt analysis
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[100%] Generating waves
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[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
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« /tmp/tmp.26C1ORPzZR/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.26C1ORPzZR/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U708_A1.txt analysis
[  0%] Built target bench
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[100%] Generating waves
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[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.ps3SYUSabL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.ps3SYUSabL/fixed.evcd » supprimé
STF_RISCV_CORE_ex_stage_i_alu_i_U701_A1.txt analysis
[  0%] Built target bench
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[100%] Generating waves
[100%] Built target rv_polito.links
[100%] Generating vectors/stim.txt
[100%] Built target rv_polito.stim.txt
[100%] Running rv_polito in ModelSim
[100%] Built target rv_polito.vsimc
« /tmp/tmp.RyV1LGpzJL/fixed.evcd » -> « dumpports_rtl.riscv_core.vcde »
« /tmp/tmp.RyV1LGpzJL/fixed.evcd » supprimé
