Embedded Flash Memory BIST based strategies to maximize test throughput and to characterize power consumption and read latency

Flash memory is an electronic non-volatile storage. Flash memory uses floating-gate transistor as a programmable element and is based on Electrically Erasable Programmable Read-Only Memory (EEPROM) technology. Microcontrollers commonly integrate embedded Flash memories (eFlash) as storage solution, because they offer an excellent balance of all critical metrics of embedded storage: read/write access times, throughput, storage permanence, capacity, density. The testing of flash memories consists in applying a sequence of program, read and erase cycles, alternating different write patterns and reading successions. Patterns and reading successions are specifically designed to trigger and detect faults. The testing process of flash memories is particularly time consuming (given the high storage capacity), and power intensive (eFlash modules occupy a large portion of the die area and require high voltages for programming and erasing). The Central Processing Unit (CPU) can perform the testing of flash memories, but Memory Built-In Self-Test (MBIST) are often integrated on-chip. A MBIST is a specialized hardware which can replace the CPU in memory testing, performing at-speed pattern verification. MBISTs reduce test time by more than two orders of magnitude compared to the CPU, at the expense of higher power consumption. Power-aware operation of MBISTs is crucial to avoid overstressing the Device Under Test (DUT). This thesis deals with the low-level API integration of the available on-chip MBIST in the test application of the next generation of Infineon Technologies AURIX microcontrollers. The focus is posed on analysis of execution time and power consumption of the test application, comparing CPU and MBIST operated testing. Furthermore, a characterization of memory access times was performed, comparing again CPU and MBIST, and substantiating predictions made at Design Time.