Deterministic Cache-Based Execution of On-Line Self-Test Routines In Multi-Core Automotive System-On-Chips

In this thesis, the author wants to discuss the problematics that arouse while working with the Self-Test procedures that are conducted online in a multicore context. Self-Test procedures have not been considered until now for their use on caches-based systems due to the lack of proof of their deterministic behavior when executing instructions. Execution in cache and deterministic are concepts considered exclusive one to each other. If we add to this conception the execution of those procedures on multicore context, the bus contention produces a strong timing unpredictable system. Having Online Self-Test procedures being executed under those conditions might lead to a variation in the fault coverage or the failure of the software test. This thesis presents a brief description of the behaviour of a test procedure in single core and multicore and purpose a cache-based strategy for achieving both deterministic behaviour and stable fault coverage from the execution of self-test procedures for multi-core systems. The proposed strategy is applied to two representative modules of the microprocessors that are affected by the issues of executing self-test software in a multi-core execution: synchronous imprecise interrupts logic and pipeline hazard detection unit. The experiment results demonstrate that it is possible to attain a stable execution whilst also improving the state-of-the-art approaches for the online testing of embedded microprocessors. The level of effectiveness of the methodology was established on all the cores of a multi-core industrial System-on-Chip (SoC) intended for automotive ASIL D applications.