UVM Environment for RISC-V processor

This thesis focuses on processor functional verification, the DUV(Device Under Verification) here is RISC-V RV32IMFCXpulp. Functional verification ensures that the implementation of a digital design is compliant with specifications before it is mass-produced. Because of the fast growth of device size and complexity, functional verification has become the bottleneck in the design process. Functional verification can take up to 70\% of the time, while the design phase requires around 30\% of the total time. In particular, the device under verification supports I-M-F-C-X extensions which are respectively Base Integer, Integer Multiplication and Division, Single Precision Floating Point, Compressed and PULP-specific. It is clear to understand that the RTL(Register-Transfer-Level) is very complex and as a result, a properly verification framework is necessary. This work is mainly based on the use of Universal Verification Methodology (UVM) to set-up a complete verification environment for RISCV processors and Python scripts to generate random stimuli accordingly to the ISA(Instruction Set Architecture). The UVM class library provides us with some of the components typically required in a verification environment such as: -The Driver, which translate the stimuli produced by the generator into the actual inputs for the design under verification. -The Monitor, which collects the internal signals of the design and its outputs to a transaction object. -The Scoreboard-checker validate that the actual results match the expected ones.